公开(公告)号：US09185316B2

公开(公告)日：2015-11-10

申请号：US13307374

申请日：2011-11-30

Applicant: Jin Min Cheon ,  Dong Hun Lee ,  Young Kyun Jeong ,  Yun Jung Kim ,  Seog Heon Ham ,  Jin Ho Seo ,  Shuichi Shimokawa

Inventor： Jin Min Cheon ,  Dong Hun Lee ,  Young Kyun Jeong ,  Yun Jung Kim ,  Seog Heon Ham ,  Jin Ho Seo ,  Shuichi Shimokawa

IPC: H01J40/14 ,  H01L27/00 ,  H03K17/78 ,  H04N5/361 ,  H04N5/365 ,  H04N5/378

CPC classification number: H04N5/361 ,  H04N5/3653 ,  H04N5/378

Abstract: A data sampler and a photo detecting apparatus compensate a reference signal with offset information measured from a unit pixel, and compare an offset-compensated reference signal with a data signal, thereby minimizing the impact of an offset occurring with an increase of gain in the data sampler.

Abstract translation: 数据采样器和光电检测装置用参考信号补偿从单位像素测得的偏移信息，并将偏移补偿参考信号与数据信号进行比较，从而最小化随着数据增益增加而发生偏移的影响 取样器。

公开(公告)号：US20130134520A1

公开(公告)日：2013-05-30

申请号：US13611759

申请日：2012-09-12

Applicant: Shigenobu Maeda ,  Hyun-pil Noh ,  Choong-ho Lee ,  Seog-heon Ham

Inventor： Shigenobu Maeda ,  Hyun-pil Noh ,  Choong-ho Lee ,  Seog-heon Ham

IPC: H01L27/088

CPC classification number: H01L21/8236 ,  H01L21/77 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L25/00 ,  H01L27/00 ,  H01L27/0883 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region.

Abstract translation: 提供了包括高压晶体管和低压晶体管的半导体器件及其制造方法。 半导体器件包括：包括高电压区域和低电压区域的半导体衬底; 形成在高电压区域中并包括第一有源区，第一源极/漏极区，第一栅极绝缘层和第一栅电极的高压晶体管; 以及形成在所述低电压区域中并包括第二有源区，第二源极/漏极区，第二栅极绝缘层和第二栅电极的低电压晶体管。 第二源极/漏极区域的厚度小于第一源极/漏极区域的厚度。

公开(公告)号：US20120097840A1

公开(公告)日：2012-04-26

申请号：US13276927

申请日：2011-10-19

Applicant: Jin Woo Kim ,  Seog Heon Ham ,  Kyung-Min Kim ,  Yong Lim

Inventor： Jin Woo Kim ,  Seog Heon Ham ,  Kyung-Min Kim ,  Yong Lim

IPC: H03M1/34 ,  H01L27/146 ,  H03M1/12

CPC classification number: H03M1/002 ,  H03M1/123 ,  H03M1/56 ,  H04N5/37213 ,  H04N5/378

Abstract: An analog-to-digital converter (ADC) within an image sensor includes a comparator comparing a ramp signal with an image signal, and a counter generating a count result in response to the comparison by counting a clock during a counting interval. The ADC determines whether a first counting interval for the counter is less than a reference interval, and if the first counting interval is less than the reference interval the counting interval is a first counting interval, else the counting interval is a second counting interval.

Abstract translation: 图像传感器内的模数转换器（ADC）包括将斜坡信号与图像信号进行比较的比较器，以及通过在计数间隔期间对时钟进行计数来产生响应于比较的计数结果的计数器。 ADC确定计数器的第一计数间隔是否小于参考间隔，并且如果第一计数间隔小于参考间隔，则计数间隔是第一计数间隔，否则计数间隔是第二计数间隔。

公开(公告)号：US20120002093A1

公开(公告)日：2012-01-05

申请号：US13171958

申请日：2011-06-29

Applicant: Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

Inventor： Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

IPC: H04N5/335 ,  H03M3/00

CPC classification number: H03M3/342 ,  H04N5/378

Abstract: A correlated double sampling circuit includes a delta-sigma modulator, a selection circuit, and an accumulation circuit. The delta-sigma modulator is configured to receive an input signal, delta-sigma modulate the input signal, and output a modulation signal. The selection circuit is configured to invert the modulation signal and selectively output one of the modulation signal and an inverted modulation signal in response to a selection signal corresponding to an operation phase. The accumulation circuit is configured to generate a first accumulation result by performing an accumulation process on one of the modulation signal and the inverted modulation signal in a first operation phase, and generate a second accumulation result by performing the accumulation process on the first accumulation result and the other one of the modulation signal and the inverted modulation signal in a second operation phase.

Abstract translation: 相关双采样电路包括Δ-Σ调制器，选择电路和累积电路。 Δ-Σ调制器被配置为接收输入信号，Δ-Σ调制输入信号，并输出调制信号。 选择电路被配置为响应于对应于操作阶段的选择信号，反转调制信号并选择性地输出调制信号和反相调制信号中的一个。 累积电路被配置为通过在第一操作阶段中对调制信号和反相调制信号之一执行累加处理来产生第一累加结果，并且通过对第一累积结果执行累积处理来生成第二累加结果，以及 在第二操作阶段中的另一个调制信号和反相调制信号。

公开(公告)号：US08059175B2

公开(公告)日：2011-11-15

申请号：US11979886

申请日：2007-11-09

Applicant: Ju-Seop Park ,  Gun-Hee Han ,  Seog-Heon Ham

Inventor： Ju-Seop Park ,  Gun-Hee Han ,  Seog-Heon Ham

IPC: H04N9/083 ,  H04N3/14 ,  H04N5/335 ,  H04N9/04

CPC classification number: H04N5/235 ,  H04N5/2355

Abstract: A method for operating an image capture device having a sensor with an array of first and second pixels includes capturing an image a plurality of times with the second pixels to produce a corresponding second image signal, the second pixels being white pixels, capturing the image a single time with the first pixels to produce a corresponding first image signal, inputting selecting signals to the sensor via a row driver to obtain the first and second image signals from the first and second pixels, respectively, and converting the first and second image signals to respective digital values via an analog-to-digital converter.

Abstract translation: 一种用于操作具有具有第一和第二像素的阵列的传感器的图像捕获装置的方法包括用第二像素捕获多次图像以产生对应的第二图像信号，第二像素为白色像素，捕获图像 与第一像素单时间产生对应的第一图像信号，经由行驱动器将选择信号输入到传感器，以分别从第一和第二像素获得第一和第二图像信号，并将第一和第二图像信号转换为 各自的数字值通过模数转换器。

公开(公告)号：US07995123B2

公开(公告)日：2011-08-09

申请号：US11877027

申请日：2007-10-23

Applicant: Dong-Myung Lee ,  Gun-Hee Han ,  Seog-Heon Ham

Inventor： Dong-Myung Lee ,  Gun-Hee Han ,  Seog-Heon Ham

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/217 ,  H03M1/12 ,  H03M1/34 ,  H03M1/56

CPC classification number: H04N5/3575 ,  H04N3/155 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/378

Abstract: A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.

Abstract translation: 公开了一种数字双采样方法，相关的互补金属氧化物半导体（CMOS）图像传感器和包括CMOS图像传感器的数字照相机。 该方法包括响应于复位信号产生对应于像素中明显的初始电压电平的第一数字数据，反转第一数字数据，输出对应于从CMOS图像传感器外部接收的图像数据的检测电压，并计数 与等于反相的第一数字数据的初始值开始的时钟信号的同步，以及响应于检测电压的电压电平的时间量。

公开(公告)号：US20110069211A1

公开(公告)日：2011-03-24

申请号：US12879684

申请日：2010-09-10

Applicant: Wun-Ki JUNG ,  Seog Heon HAM ,  Dong Hun LEE ,  Kwi Sung YOO ,  Min Ho KWON

Inventor： Wun-Ki JUNG ,  Seog Heon HAM ,  Dong Hun LEE ,  Kwi Sung YOO ,  Min Ho KWON

IPC: H04N5/335 ,  H03M3/00

CPC classification number: H04N5/378 ,  H03M3/48

Abstract: Example embodiments are directed to an analog-to-digital converter (ADC) that controls a gain by changing a system parameter, an image sensor including the ADC and a method of operating the ADC. The ADC includes a sigma-delta modulator which receives an input signal and a clock signal and sigma-delta modulates the input signal into a digital output signal based on the clock signal and an accumulation unit which accumulates the digital output signal at each cycle of the clock signal according to an analog-to-digital conversion time and outputs an accumulation result. A system parameter is varied during the analog-to-digital conversion time to control a gain of the ADC. The method of operating the analog-to-digital converter includes sigma-delta modulating an input signal into a digital output signal in response to a clock signal input to the ADC; and accumulating the digital output signal at each cycle of the input clock signal according to an analog-to-digital conversion time and outputting an accumulation result.

Abstract translation: 示例性实施例针对通过改变系统参数来控制增益的模数转换器（ADC），包括ADC的图像传感器和操作ADC的方法。 ADC包括Σ-Δ调制器，其接收输入信号和时钟信号，并且Σ-Δ基于时钟信号将输入信号调制成数字输出信号;以及累积单元，其在每个周期的每个周期累积数字输出信号 时钟信号，并输出累积结果。 在模数转换时间期间，系统参数会发生变化，以控制ADC的增益。 操作模数转换器的方法包括响应于输入到ADC的时钟信号而将输入信号Σ-Δ调制成数字输出信号; 并且根据模数转换时间在输入时钟信号的每个周期累加数字输出信号，并输出累加结果。

公开(公告)号：US20110069191A1

公开(公告)日：2011-03-24

申请号：US12801999

申请日：2010-07-07

Applicant: Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

Inventor： Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

IPC: H04N5/225 ,  H04N5/335 ,  H01L27/00 ,  H03L7/06

CPC classification number: H04N5/3575 ,  H04N5/374 ,  H04N5/378

Abstract: A correlated double sampling (CDS) circuit is provided. The CDS circuit is configured to perform a CDS on a reset signal and an image signal during a CDS phase respectively. The CDS circuit includes a sampling circuit configured to output a difference between a correlated double sampled reset signal and a correlated double sampled image signal, and a feedback unit configured to feedback the difference output from the sampling circuit during a PGA phase to an input of the sampling circuit.

Abstract translation: 提供了相关的双重采样（CDS）电路。 CDS电路被配置为在CDS阶段期间在复位信号和图像信号上执行CDS。 CDS电路包括：采样电路，被配置为输出相关的双采样复位信号和相关的双采样图像信号之间的差;以及反馈单元，被配置为将在PGA阶段期间从采样电路输出的差值反馈到 采样电路。

公开(公告)号：US20110050473A1

公开(公告)日：2011-03-03

申请号：US12801062

申请日：2010-05-20

Applicant: Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

Inventor： Wun-Ki Jung ,  Seog Heon Ham ,  Dong Hun Lee ,  Kwi Sung Yoo ,  Min Ho Kwon

IPC: H03M3/00

CPC classification number: H03M3/356 ,  H03M3/458

Abstract: An analog-digital converter (ADC) includes a correlated double sampling (CDS) circuit configured to perform CDS on each of a reset signal and an image signal output from a pixel to generate a correlated double sampled reset signal and a correlated double sampled image signal, respectively. A delta sigma (ΔΣ) ADC, also included in the ADC, is configured to output a difference between a first digital code that is generated by performing ΔΣ analog-digital conversion on the correlated double sampled reset signal and a second digital code that is generated by performing ΔΣ analog-digital conversion on the correlated double sampled image signal.

Abstract translation: 模拟数字转换器（ADC）包括相关双采样（CDS）电路，其被配置为在复位信号和从像素输出的图像信号中的每一个上执行CDS，以产生相关的双采样复位信号和相关的双采样图像信号 ， 分别。 还包括在ADC中的Δ西格玛（＆Dgr;＆Sgr）ADC被配置为输出通过执行＆Dgr＆amp; Sgr生成的第一数字代码之间的差异。 对相关的双重采样复位信号进行模拟数字转换和通过执行＆Dgr＆amp; 对相关双采样图像信号进行模数转换。

公开(公告)号：US20090289823A1

公开(公告)日：2009-11-26

申请号：US12453845

申请日：2009-05-26

Applicant: Youngcheol Chae ,  In Hee Lee ,  Gunhee Han ,  Seog Heon Ham

Inventor： Youngcheol Chae ,  In Hee Lee ,  Gunhee Han ,  Seog Heon Ham

IPC: H03M3/00

CPC classification number: H03M3/384 ,  H03M3/424

Abstract: A sigma-delta analog-to-digital converter may include a sigma-delta modulator and a decimation filter. The sigma-delta modulator may convert a first analog input signal into a first bit stream having a first pattern using sigma-delta modulation and convert a second analog input signal into a second bit stream having a second pattern using the sigma-delta modulation. The decimation filter may integrate the number of bits having a particular value in the first bit stream, output a first digital value, calculate a bitwise complement value of the first digital value, integrate the number of bits having the particular value in the second bit stream with the bitwise complement value of the first digital value as an initial value of a second digital value, and output the second digital value.

Abstract translation: Σ-Δ模数转换器可以包括Σ-Δ调制器和抽取滤波器。 Σ-Δ调制器可以使用Σ-Δ调制将第一模拟输入信号转换成具有第一模式的第一比特流，并且使用Σ-Δ调制将第二模拟输入信号转换成具有第二模式的第二比特流。 抽取滤波器可以将具有特定值的比特数量集成在第一比特流中，输出第一数字值，计算第一数字值的按位补码，将具有特定值的比特数集成在第二比特流中 以第一数字值的按位补码作为第二数字值的初始值，并输出第二数字值。