公开(公告)号：US08619464B1

公开(公告)日：2013-12-31

申请号：US13219537

申请日：2011-08-26

Applicant: Shankar Sinha ,  Brian Wong ,  Shih-Lin S. Lee ,  Abhishek Sharma

Inventor： Shankar Sinha ,  Brian Wong ,  Shih-Lin S. Lee ,  Abhishek Sharma

IPC: G11C11/00

CPC classification number: G11C7/02 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1104

Abstract: Integrated circuits may have arrays of memory elements. Data may be loaded into the memory elements and read from the memory elements using data lines. Address lines may be used to apply address signals to write address transistors and read circuitry. A memory element may include a bistable storage element. Read circuitry may be coupled between the bistable storage element and a data line. The read circuitry may include a data storage node. A capacitor may be coupled between the data storage node and ground and may be used in storing preloaded data from the bistable storage element. The read circuitry may include a transistor that is coupled between the bistable storage element and the data storage node and a transistor that is coupled between the data storage node and the data line.

Abstract translation: 集成电路可以具有存储元件阵列。 数据可以被加载到存储器元件中并且使用数据线从存储器元件读取。 地址线可以用于施加地址信号以写入地址晶体管和读取电路。 存储元件可以包括双稳态存储元件。 读取电路可以耦合在双稳态存储元件和数据线之间。 所述读取电路可以包括数据存储节点。 电容器可以耦合在数据存储节点和地之间，并且可以用于存储来自双稳态存储元件的预加载的数据。 读取电路可以包括耦合在双稳态存储元件和数据存储节点之间的晶体管，以及耦合在数据存储节点和数据线之间的晶体管。

公开(公告)号：US07678674B1

公开(公告)日：2010-03-16

申请号：US11211509

申请日：2005-08-26

Applicant: Shankar Sinha ,  Ashot Melik-Martirosian ,  Ihsan Djomehri

Inventor： Shankar Sinha ,  Ashot Melik-Martirosian ,  Ihsan Djomehri

IPC: H01L21/425

CPC classification number: H01L21/26586 ,  H01L27/11568 ,  H01L29/1083 ,  H01L29/792

Abstract: A method of forming implants for a memory cell includes forming an oxide-nitride-oxide (ONO) stack over a substrate and implanting first impurities in the substrate adjacent each side of the ONO stack using a first implantation energy and a first tilt angle to produce first pocket implants. The method further includes implanting second impurities in the substrate adjacent each side of the ONO stack using a second implantation energy and a second tilt angle to produce second pocket implants, where the second implantation energy is substantially larger than the first implantation energy and where the second tilt angle is substantially larger than the first tilt angle.

Abstract translation: 用于形成存储器单元的种植体的方法包括在衬底上形成氧化物 - 氧化物 - 氧化物（ONO）堆叠，并且使用第一注入能量和第一倾斜角度在邻近ONO堆叠的每一侧的基板中注入第一杂质，以产生 第一口袋种植体。 该方法还包括使用第二注入能量和第二倾斜角度在邻近ONO堆叠的每一侧的衬底中注入第二杂质以产生第二袋植入物，其中第二注入能量基本上大于第一注入能量，其中第二种植入能量 倾斜角大致大于第一倾斜角。

公开(公告)号：US20090256242A1

公开(公告)日：2009-10-15

申请号：US12102488

申请日：2008-04-14

Applicant: Suketu Arun Parikh ,  Olov B. Karlsson ,  Yu Sun ,  Shankar Sinha ,  Timothy Thurgate

Inventor： Suketu Arun Parikh ,  Olov B. Karlsson ,  Yu Sun ,  Shankar Sinha ,  Timothy Thurgate

IPC: H01L21/425 ,  H01L23/58

CPC classification number: H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1041 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.

Abstract translation: 一种形成电子器件的方法，包括在包括衬底的工件中形成第一沟槽，所述第一沟槽具有侧壁和在所述侧壁之间延伸宽度的底表面，并且沿着所述侧壁和底部形成电荷存储层 第一沟槽的表面。 该方法还包括在第一沟槽的底表面下方的衬底内注入离子以形成植入区域并退火植入区域，其中在退火之后，植入区域延伸底表面的宽度并沿着侧壁的一部分 。

公开(公告)号：US20080135902A1

公开(公告)日：2008-06-12

申请号：US11634777

申请日：2006-12-06

Applicant: Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

Inventor： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

IPC: H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L29/66833 ,  H01L21/26506 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

Abstract translation: 本发明的一个实施例涉及一种存储单元。 存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。 存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。 阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。 还公开了其他实施例。

公开(公告)号：US20080123384A1

公开(公告)日：2008-05-29

申请号：US11465701

申请日：2006-08-18

Applicant: Mark RANDOLPH ,  Zhizheng LIU ,  Ashot MELIK-MARTIROSIAN ,  Yi HE ,  Shankar SINHA

Inventor： Mark RANDOLPH ,  Zhizheng LIU ,  Ashot MELIK-MARTIROSIAN ,  Yi HE ,  Shankar SINHA

IPC: G11C5/02

CPC classification number: G11C5/063 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

Abstract: A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.

Abstract translation: 半导体器件包括核心存储器阵列和周边区域。 核心存储器阵列区域包括一组存储器单元。 外围区域包括一组选择晶体管。 选择晶体管以与芯存储器阵列中的存储器单元基本相同的间距形成并具有基本上相同的沟道长度。

公开(公告)号：US20070008782A1

公开(公告)日：2007-01-11

申请号：US11174560

申请日：2005-07-06

Applicant: Shankar Sinha ,  Zhizheng Liu ,  Yi He

Inventor： Shankar Sinha ,  Zhizheng Liu ,  Yi He

IPC: G11C16/04

CPC classification number: H01L29/7923 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias to a source region associated with the memory cell and/or applying a negative bias to a substrate region associated with the memory cell.

Abstract translation: 一种对非易失性存储器件中的存储器单元进行编程的方法包括：将第一电压施加到与存储器单元相关联的控制栅极，并将第二电压施加到与存储器单元相关联的漏极区域。 该方法还包括向与存储器单元相关联的源极区域施加正偏压和/或将负偏压施加到与存储器单元相关联的衬底区域。

公开(公告)号：US06642119B1

公开(公告)日：2003-11-04

申请号：US10215171

申请日：2002-08-08

Applicant: Mario M. Pelella ,  Shankar Sinha ,  Simon S. Chan

Inventor： Mario M. Pelella ,  Shankar Sinha ,  Simon S. Chan

IPC: H01L21336

CPC classification number: H01L29/66507 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78612 ,  H01L29/78621 ,  Y10S438/952

Abstract: The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.

Abstract translation: 本发明涉及一种形成晶体管和晶体管结构的方法。 本发明包括使用双硅化物工艺来形成晶体管，当与SOI型器件结构结合使用时，其降低电阻并降低浮体效应。

公开(公告)号：US08755218B2

公开(公告)日：2014-06-17

申请号：US13149249

申请日：2011-05-31

Applicant: Shih-Lin S. Lee ,  Peter J. McElheny ,  Preminder Singh ,  Shankar Sinha

Inventor： Shih-Lin S. Lee ,  Peter J. McElheny ,  Preminder Singh ,  Shankar Sinha

IPC: G11C11/00

CPC classification number: G11C7/00 ,  G06F12/1425 ,  G11C8/16 ,  G11C2029/0411

Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Abstract translation: 可以提供具有多端口存储器元件的集成电路。 多端口存储元件可以包括锁存电路，第一组地址晶体管和第二组地址晶体管。 锁存电路可以包括交叉耦合的反相器，每个反相器包括上拉晶体管和下拉晶体管。 第一组地址晶体管可以将锁存电路耦合到写入端口，而第二组地址晶体管可以将锁存电路耦合到读取端口。 下拉晶体管和第二组地址晶体管可以具有由控制信号控制的体偏置端子。 在数据加载操作期间，控制信号可以临时升高以削弱下拉晶体管和第二组地址晶体管，以改善多端口存储器元件的写入裕度。

公开(公告)号：US08638594B1

公开(公告)日：2014-01-28

申请号：US13110823

申请日：2011-05-18

Applicant: Shankar Sinha ,  Shih-Lin S. Lee ,  Peter J. McElheny

Inventor： Shankar Sinha ,  Shih-Lin S. Lee ,  Peter J. McElheny

IPC: G11C11/00 ,  H01L21/02

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104

Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.

Abstract translation: 提供具有存储元件的集成电路。 存储元件可以包括通过存取晶体管耦合到数据线的存储电路。 存取晶体管可用于从存储电路读取数据并将数据写入存储电路。 存取晶体管可以具有不对称的源极 - 漏极电阻。 存取晶体管可以具有耦合到数据线的第一源极 - 漏极和耦合到存储电路的第二源极 - 漏极。 第二源极 - 漏极可以具有大于与第一源极 - 漏极相关联的接触电阻的接触电阻。 具有不对称源极 - 漏极电阻的存取晶体管在通过高信号到存储电路时通过低信号和第二驱动强度时可具有第一驱动强度。 第二驱动强度可能小于第一驱动强度。 具有非对称驱动强度的存取晶体管可用于提高存储器读/写性能。

公开(公告)号：US08218353B1

公开(公告)日：2012-07-10

申请号：US12561236

申请日：2009-09-16

Applicant: Jun Liu ,  Shankar Sinha ,  Qi Xiang ,  Yow-Juang Liu

Inventor： Jun Liu ,  Shankar Sinha ,  Qi Xiang ,  Yow-Juang Liu

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.

Abstract translation: 提供具有存储元件的集成电路。 存储器元件可以被布置在存储器块中。 存储器块可以包括存储数据的交叉耦合的反相器。 存储的数据可用于编程传输晶体管。 存储器块中的晶体管可能受到压力。 根据所使用的应力诱导层的类型，可以将内部的拉伸应力或压应力内置到晶体管中。 受压的晶体管可能有助于提高存储器块的布线速度。 可以使用双栅极氧化工艺来实施受压晶体管。