Abstract:
The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).
Abstract:
A system includes a host, first and second devices which operate as an acting device and a standby device, and a simplex unit controlled by the acting device. Each device is provided with a monitoring unit for monitoring the occurrence of failure, means for notifying the other device of a failure in its own device, and active/standby notification means. The active/standby notification means notifies the simplex unit that its own device is acting or standing by when the device becomes the acting device or standby device in response to a command from the host. Upon a failure in the other device when its own device is standing by, the active/standby notification means notifies the simplex unit that its own device is now an apparent acting device. Upon a failure in its own device when its own device is acting, the active/standby notification means notifies the simplex unit that its own device is now an apparent standby device. The simplex unit executes predetermined control upon accepting control data from the apparent acting device.
Abstract:
An information processing system includes a simplex system and a duplex system in which at least two data transmitting systems are provided each capable of being an act system or a standby system. Each data transmitting system has a data acquiring unit. The simplex system includes a controller for controlling a selector to switch between the systems. When in a standby condition, the data acquiring unit of the respective data transmitting system in the duplex system issues an access request signal to a switching signal generating unit provided in the controller of the simplex system to request that the output of the selector be switched from the act system to the standby system in the duplex system. Upon receipt of the access request signal from the data acquiring unit in the standby system, the switching signal generating unit switches the selector to the standby system. As a result, status data acquired by the data acquiring unit in the simplex section is output to the data acquiring section in the standby system. The duplex system uses the status data to make a diagnosis of the standby system for its normality.
Abstract:
A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
Abstract:
A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.
Abstract:
A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
Abstract:
Four SR modules are provided in the second stage of a 3-stage MSSR switch. To guarantee the MSSR switch the capacity of 20 Gbps, SR modules are provided in each of the first and third stages of the switch. When the capacity of the MSSR switch is extended from 20 Gbps to 40 Gbps, SR modules are added to both of the first and third stages and connected to the four SR modules in the second stage. To further extend the capacity of the MSSR switch to 60 or 80 Gbps, the SR modules are sequentially added to the first and third stages, and the newly provided SR modules are connected to the four SR modules in the second stage.
Abstract:
A sending trunk on the input side of an ATM switch is equipped with a test cell generating section, and a receiving trunk on the output side of the ATM switch is equipped with a test cell detecting section. The test cell generating section includes a unit for setting a test cell identifier in the header of a test cell and a unit for generating pieces of data with regularity in the information field of the test cell. The test cell detecting section includes a unit for detecting the test cell identifier from the header of a cell received and a unit for detecting regularity from data in the information field of the cell received. When a test cell is transmitted, the test cell detecting section evaluates the result of a test on the basis of the result of detection of the test cell identifier from the header of the test cell and the result of detection of the regularity from data in the information field of the test cell.
Abstract:
A CRC operating unit which performs a CRC operation on received data using as an initial value a CRC operation result actual value obtained in a previous operation, and outputs a CRC operation result actual value. A delay unit delays the CRC operation result actual value by the time taken for a header part to be entered. The CRC operation result derivation unit outputs as a CRC operation result derivation value an operation result obtained by a CRC operation performed for all the receiving data of a header part provided with the above described CRC code using the CRC operation result actual value as an initial value. The coincidence detecting unit compares the CRC operation result actual value with the CRC operation result derivation value to detect the input timing of a header part as coincident timing for both values.
Abstract:
A communications apparatus for switching among different interfaces includes a switch unit. The switch unit includes a main switch for switching data of a fixed length and an interface having a first buffer for an input of the main switch and a second buffer for an output of the main switch.