公开(公告)号：US20110255328A1

公开(公告)日：2011-10-20

申请号：US13170645

申请日：2011-06-28

申请人： Yasuo MURAKUKI ,  Shunichi IWANARI ,  Yoshiaki NAKAO

发明人： Yasuo MURAKUKI ,  Shunichi IWANARI ,  Yoshiaki NAKAO

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： H01L27/105 ,  H01L27/0207 ,  H01L27/11509 ,  H01L28/55

摘要： The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device.

摘要翻译： 减小半导体存储器件的尺寸和集成程度的需求增加。 在半导体存储器件中，必须在其中提供用于稳定电源电压等的平滑电容器形成在存储单元A和B的下层中以与彼此相邻的两个存储单元A和B重叠。 因此，能够减小由容量大的平滑电容器占有的面积，提高积分度，能够在半导体存储装置中设置容量大的平滑电容器。

公开(公告)号：US07835169B2

公开(公告)日：2010-11-16

申请号：US12368622

申请日：2009-02-10

申请人： Yasuo Murakuki ,  Yasushi Gohou ,  Shunichi Iwanari ,  Masanori Matsuura ,  Yoshiaki Nakao

发明人： Yasuo Murakuki ,  Yasushi Gohou ,  Shunichi Iwanari ,  Masanori Matsuura ,  Yoshiaki Nakao

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.

摘要翻译： 半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括以矩阵图案排列的多个存储单元，以及多个存储单元阵列共享的单元板板线，每个单元板线对应于 存储单元的行和每个单元格板线连接到相应行之一的存储单元。 每个存储单元阵列包括多个字线，每个字线对应于存储单元阵列中存​​储单元的行中的每一行。 连接到每个单元格板行的存储单元的数量大于连接到与每个单元格板行相对应的一个字线的存储单元的数量。

公开(公告)号：US20090175065A1

公开(公告)日：2009-07-09

申请号：US12259639

申请日：2008-10-28

申请人： Yoshiaki NAKAO ,  Yasushi GOHOU ,  Shunichi IWANARI ,  Yasuo MURAKUKI ,  Masanori MATSUURA

发明人： Yoshiaki NAKAO ,  Yasushi GOHOU ,  Shunichi IWANARI ,  Yasuo MURAKUKI ,  Masanori MATSUURA

IPC分类号： G11C11/22 ,  G11C17/16 ,  H01S4/00 ,  G11C7/00

CPC分类号： G11C11/22 ,  H01L27/11509 ,  H01L27/11592 ,  Y10T29/49002

摘要： A semiconductor memory device including a ferroelectric memory includes: a nonvolatile memory having higher data retention capability under high temperature than the ferroelectric memory; and a connection circuit for switching between connection and disconnection of the ferroelectric memory and the nonvolatile memory. The ferroelectric memory receives, through the connection circuit, at least part of data which is unique to the device and which has been written into the nonvolatile memory, and retains the received data.

摘要翻译： 包括铁电存储器的半导体存储器件包括：在高温下比铁电存储器具有更高数据保持能力的非易失性存储器; 以及用于在铁电存储器和非易失性存储器的连接和断开之间切换的连接电路。 铁电存储器通过连接电路接收设备唯一且被写入到非易失性存储器中的至少部分数据，并保留接收的数据。

公开(公告)号：US20080313391A1

公开(公告)日：2008-12-18

申请号：US12136340

申请日：2008-06-10

申请人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

发明人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

IPC分类号： G06F12/02

CPC分类号： G11C16/26 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1063

摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

摘要翻译： 一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作 块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

公开(公告)号：US20070279960A1

公开(公告)日：2007-12-06

申请号：US11878971

申请日：2007-07-30

申请人： Shunichi Iwanari

发明人： Shunichi Iwanari

IPC分类号： G11C11/22

CPC分类号： G11C5/143 ,  G11C11/22 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/0407 ,  G11C2029/5002

摘要： A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time, When power is turned on, the set data that are stored in the ferroelectric memory are stored and retained in a latch circuit by a control circuit. Based on the set data retained in the latch circuit, data writing is performed in the ferroelectric memory respectively in the power-on state and in the power-off instruction time. Thus, operations of the ferroelectric memory can be controlled with desired operation timings according to operating conditions for each memory system. Excessive stress application to the ferroelectric memory during the power-on state is prevented and endurance deterioration is suppressed, while data retention characteristics after power-off are improved.

摘要翻译： 提供在存储器系统中的铁电存储器预先存储用于数据写入时间的数据到存储器单元。 设定数据包括在通电状态和断电指令时间之间不同的两种数据。当电源接通时，存储在强电介质存储器中的设定数据被存储并保存在锁存电路中 通过控制电路。 基于保持在锁存电路中的设定数据，分别在电源接通状态和断电指示时刻的铁电存储器中进行数据写入。 因此，可以根据每个存储器系统的操作条件以期望的操作定时来控制铁电存储器的操作。 防止在通电状态下对铁电存储器施加过大的应力，并且抑制耐久性劣化，同时提高断电后的数据保持特性。

公开(公告)号：US07085148B2

公开(公告)日：2006-08-01

申请号：US10937441

申请日：2004-09-10

申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Yasuo Murakuki

发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Yasuo Murakuki

IPC分类号： G11C7/06

CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C11/22

摘要： A semiconductor memory device having a semiconductor substrate includes a plurality of reference cells 4 and a plurality of bit lines 10. The reference cells 4 are formed in a region near the centerline of a predetermined region of the semiconductor substrate which is perpendicular to the bit lines 10. The bit lines 10 form pairs each composed of two adjacent bit lines. Two bit lines 10 in each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state. Each pair of bit lines 10 has at least one cross section 11 where one of the pair of bit lines 10 crosses the other, to switch between the first parallel state and the second parallel state. The cross section 11 is provided in the predetermined region of the semiconductor substrate such that the length of a bit line 10 in the first parallel state is equal to the length of the bit line 10 in the second parallel state. The semiconductor memory device is reduced in size.

摘要翻译： 具有半导体衬底的半导体存储器件包括多个参考单元4和多个位线10。 参考单元4形成在半导体衬底的垂直于位线10的预定区域的中心线附近的区域中。 位线10形成每对由两个相邻位线组成的对。 每对中的两个位线10具有第一并联状态和第二并行状态，其中两个位线的位置与第一并行状态相反。 每对位线10具有至少一个横截面11，其中一对位线10中的一个与另一个位线交叉，以在第一并行状态和第二平行状态之间切换。 横截面11设置在半导体衬底的预定区域中，使得位于第一并联状态的位线10的长度等于位线10在第二平行状态下的长度。 半导体存储器件的尺寸减小。

公开(公告)号：US06522567B2

公开(公告)日：2003-02-18

申请号：US09874833

申请日：2001-06-05

申请人： Shunichi Iwanari

发明人： Shunichi Iwanari

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A method and circuit are provided that can compensate for the various types of fatigue and degradation, including an imprint phenomenon, even under a variety of working conditions after a ferroelectric memory actually has been shipped as a product. The circuit includes a plurality of memory cell degradation detectors, a comparator, and a power supply circuit. Each of the memory cell degradation detectors has a plurality of data holding circuits that differ in capacitance ratio of a dummy bit line (Cb) to a dummy memory cell (Cs). The comparator compares signals from the memory cell degradation detectors to expected values. The power supply circuit changes a value of the voltage applied to the memory cell based on the signal from the comparator, provided as the result of comparison showing that the signals do not agree with the expected values. Thus, the fatigue and degradation of the ferroelectric memory cell can be detected so as to adjust the voltage to be applied to the memory cell during reading/writing.

公开(公告)号：US5818782A

公开(公告)日：1998-10-06

申请号：US814507

申请日：1997-03-10

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C13/00

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

公开(公告)号：US5546346A

公开(公告)日：1996-08-13

申请号：US354124

申请日：1994-12-06

申请人： Masashi Agata ,  Kazuhiro Matsuyama ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

发明人： Masashi Agata ,  Kazuhiro Matsuyama ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM has following: a first precharge circuit for precharging or voltage-equalizing the DQ-line pair to a power supply voltage level in the first and forth periods only; a second precharge circuit for voltage-equalizing the DBI-line pair to a ground voltage level in the first and second periods only; a third precharge circuit for voltage-equalizing the RDB-line pair to the power supply voltage level in the first and second periods only; first and second differential amplifiers for transmitting data on the DQ lines onto the DBI lines in the third period and for holding the data on the DBI lines in the fourth period; and a third differential amplifier which transmits the data on the DBI lines onto the RDB lines in the third period and which holds the data on the RDB lines in the fourth period.

摘要翻译： 在需要与时钟信号同步执行高速连续操作的同步DRAM中，DBI线对连接在DQ线对和RDB线对之间，其流水线操作的单周期时间为 分为四个阶段。 该S-DRAM具有以下：第一预充电电路，用于仅在第一和第四周期中将DQ线对预充电或电压均衡至电源电压电平; 第二预充电电路，用于仅在第一和第二周期中将DBI线对对电压均衡至接地电压电平; 第三预充电电路，用于仅在第一和第二周期中将RDB线对对电压均衡至电源电压电平; 第一和第二差分放大器，用于在第三周期中将DQ线上的数据发送到DBI线上，并且用于在第四周期中将数据保存在DBI线上; 以及第三差分放大器，其在第三周期中将DBI线上的数据发送到RDB线上，并且在第四周期中将数据保存在RDB线上。

公开(公告)号：US08446751B2

公开(公告)日：2013-05-21

申请号：US13170645

申请日：2011-06-28

申请人： Yasuo Murakuki ,  Shunichi Iwanari ,  Yoshiaki Nakao

发明人： Yasuo Murakuki ,  Shunichi Iwanari ,  Yoshiaki Nakao

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C5/10 ,  G11C7/02 ,  G11C11/22 ,  G11C11/24

CPC分类号： H01L27/105 ,  H01L27/0207 ,  H01L27/11509 ,  H01L28/55

摘要： The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device.

摘要翻译： 减小半导体存储器件的尺寸和集成程度的需求增加。 在半导体存储器件中，必须在其中提供用于稳定电源电压等的平滑电容器形成在存储单元A和B的下层中以与彼此相邻的两个存储单元A和B重叠。 因此，能够减小由容量大的平滑电容器占有的面积，提高积分度，能够在半导体存储装置中设置容量大的平滑电容器。