公开(公告)号：US5097441A

公开(公告)日：1992-03-17

申请号：US501758

申请日：1990-03-30

Applicant: Soo-In Cho ,  Dong-Il Shu ,  Dong-Sun Min ,  Young-Rae Kim

Inventor： Soo-In Cho ,  Dong-Il Shu ,  Dong-Sun Min ,  Young-Rae Kim

IPC: G11C11/401 ,  G11C5/06 ,  G11C8/14 ,  G11C11/34 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC classification number: G11C5/063 ,  G11C8/14 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/528 ,  H01L2924/0002

Abstract: A higher packing of cells in a memory circuit includes a plurality of word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.

Abstract translation: 存储器电路中的单元的更高的封装包括采用多个字线，多个位线和各种解码器的多个字线驱动器。 公开了字线驱动器的阵列方法，其可以减小字线驱动器之间的间距，使得可以容易地实现半导体存储器阵列的布局。 此外，建议存储阵列的其他组件的阵列方法。

公开(公告)号：US07483320B2

公开(公告)日：2009-01-27

申请号：US11266154

申请日：2005-11-03

Applicant: Sang-Man Byun ,  Soo-In Cho ,  Sang-Seok Kang

Inventor： Sang-Man Byun ,  Soo-In Cho ,  Sang-Seok Kang

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/48 ,  G11C29/1201

Abstract: In a method of inputting/outputting data in a semiconductor memory device, first data and second data are buffered and outputted to a first output node and a second output node, respectively, in a normal mode. In a test mode, the first data is buffered through a first transmission line and a second transmission line and outputted to the first output node and the second output node in response to at least one control signal. Also, in the test mode, the second data is buffered through the first transmission line and the second transmission line and outputted to the first output node and the second output node in response to the at least one control signal. Accordingly, test time may be reduced, and variations of operation characteristics caused by merging the data pins may also be reduced.

Abstract translation: 在半导体存储器件中输入/输出数据的方法中，第一数据和第二数据被缓冲并分别以正常模式输出到第一输出节点和第二输出节点。 在测试模式中，第一数据通过第一传输线和第二传输线进行缓冲，并响应于至少一个控制信号被输出到第一输出节点和第二输出节点。 此外，在测试模式中，第二数据通过第一传输线和第二传输线缓冲，并且响应于至少一个控制信号被输出到第一输出节点和第二输出节点。 因此，可以减少测试时间，并且还可以减少由数据引脚合并引起的操作特性的变化。

公开(公告)号：US5889719A

公开(公告)日：1999-03-30

申请号：US511812

申请日：1995-08-07

Applicant: Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

Inventor： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

IPC: G11C5/14 ,  H02M3/07 ,  G11C13/00

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

公开(公告)号：US5214600A

公开(公告)日：1993-05-25

申请号：US836159

申请日：1992-02-24

Applicant: Soo-In Cho ,  Dong-Il Shu ,  Hong-Sun Hwang

Inventor： Soo-In Cho ,  Dong-Il Shu ,  Hong-Sun Hwang

IPC: G11C7/18

CPC classification number: G11C7/18

Abstract: Disclosed is a layout method for increasing pitches between bit lines and between sense amplifiers so as to easily accomplish fabrication of a semiconductor memory device and a semiconductor memory array capable of reducing the number of sense amplifiers. The semiconductor memory array includes a plurality of bit lines, and a plurality of sense amplifiers, each sense amplifier being connected to each pair of the bit lines, wherein the sense amplifiers placed in each column make up each group, with odd pairs of the bit lines being connected to even or odd sense amplifier groups, and even pairs of the bit lines being connected to even or odd sense amplifier groups.

Abstract translation: 公开了一种用于增加位线之间和读出放大器之间的间距的布局方法，以便容易地实现能够减少读出放大器数量的半导体存储器件和半导体存储器阵列的制造。 半导体存储器阵列包括多个位线，以及多个读出放大器，每个读出放大器连接到每对位线，其中放置在每列中的读出放大器组成每组，奇数位对 线连接到偶或奇检测放大器组，并且偶数对的位线连接到偶校验放大器组或奇检测放大器组。

公开(公告)号：US5140553A

公开(公告)日：1992-08-18

申请号：US470834

申请日：1990-01-26

Applicant: Hoon Choi ,  Soo-In Cho

Inventor： Hoon Choi ,  Soo-In Cho

IPC: G11C29/00 ,  G11C11/401 ,  G11C11/4072 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/34

CPC classification number: G11C11/4094 ,  G11C11/4072 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/34

Abstract: A flash writing circuit for testing of dynamic random access memory (DRAM) devices comprises a generally conventional DRAM device and includes additional elements for writing identical data in each memory cell via bit lines connected to the memory cells but without the use of the conventional I/O lines normally used to write data into the memory cells.

Abstract translation: 用于测试动态随机存取存储器（DRAM）器件的闪存写入电路包括通常为常规的DRAM器件，并且包括用于通过连接到存储器单元的位线在每个存储器单元中写入相同数据的附加元件，但不使用常规I / O线通常用于将数据写入存储单元。

公开(公告)号：US5933379A

公开(公告)日：1999-08-03

申请号：US52053

申请日：1998-03-30

Applicant: Churoo Park ,  Soo-In Cho

Inventor： Churoo Park ,  Soo-In Cho

IPC: G11C29/50 ,  G11C29/56 ,  G11C7/00

CPC classification number: G11C29/50 ,  G11C29/56 ,  G11C11/401

Abstract: A circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency "n" times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.

Abstract translation: 用于测试半导体存储器件的电路包括用于控制外部时钟信号的等待时间的等待时间控制器，用于在存储器件中产生列地址信号的内部列地址发生器和用于产生模式信号的模式寄存器。 用于测试半导体存储器件的电路还包括用于解码内部列地址发生器的输出地址信号的列地址解码器，用于读取或写入数据的存储单元，用于控制数据输入/输出的输入/输出控制单元 存储单元根据等待时间控制器的输出信号，数据输入缓冲器和数据输出缓冲器。 还提供了一种用于产生具有外部时钟信号频率“n”倍的内部时钟信号的倍频器。 通过提供上述改进，常规测试设备可用于测试高频存储器件。

公开(公告)号：US5790465A

公开(公告)日：1998-08-04

申请号：US714577

申请日：1996-09-16

Applicant: Jae-gu Roh ,  Soo-in Cho

Inventor： Jae-gu Roh ,  Soo-in Cho

IPC: G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/34

Abstract: A burn-in test circuit of a semiconductor memory device with a first test circuit having output terminals connected to input terminals of a first half of plurality of word line drivers. A second test circuit has output terminals connected to input terminals of a second half of the plurality of word line drivers. The first and second tests circuits are sequentially activated to perform a burn-in test for all the memory cells.

Abstract translation: 一种具有第一测试电路的半导体存储器件的老化测试电路，其具有连接到多个字线驱动器的前半部分的输入端的输出端子。 第二测试电路具有连接到多个字线驱动器的后半部分的输入端子的输出端子。 第一和第二测试电路被顺序激活，以对所有存储器单元执行老化测试。

公开(公告)号：US5726939A

公开(公告)日：1998-03-10

申请号：US668952

申请日：1996-06-24

Applicant: Soo-In Cho ,  Jung-Hwa Lee

Inventor： Soo-In Cho ,  Jung-Hwa Lee

IPC: G11C11/401 ,  G11C8/12 ,  G11C29/00 ,  G11C29/34 ,  G11C13/00

CPC classification number: G11C8/12

Abstract: The time required for testing high-density semiconductor memory devices is reduced by circuits and methodology for rapidly writing test data bits into the memory array. A common word line enable signal is arranged to turn on all of the word lines in the array simultaneously. Test data bits are applied to the array by gating them onto the I/O lines so that separate test bit lines are not required. A fast test enable signal gates the test bits onto the I/O lines in all columns of the array simultaneously, so that all of the memory cells receive test bits at one time. The new circuitry has the further advantages of reduced area and capacitance, the latter further contributing to reducing the test data write time.

Abstract translation: 通过用于将测试数据位快速写入存储器阵列的电路和方法来减少测试高密度半导体存储器件所需的时间。 公共字线使能信号被布置成同时打开阵列中的所有字线。 测试数据位通过将它们门控到I / O线上来应用于阵列，以便不需要单独的测试位线。 快速测试使能信号同时将测试位门控在阵列的所有列中的I / O线上，以便所有存储单元一次接收测试位。 新电路具有减小面积和电容的进一步优点，后者进一步有助于减少测试数据写入时间。

公开(公告)号：US20060092723A1

公开(公告)日：2006-05-04

申请号：US11266154

申请日：2005-11-03

Applicant: Sang-Man Byun ,  Soo-In Cho ,  Sang-Seok Kang

Inventor： Sang-Man Byun ,  Soo-In Cho ,  Sang-Seok Kang

IPC: G11C7/00

CPC classification number: G11C29/48 ,  G11C29/1201

Abstract: In a method of inputting/outputting data in a semiconductor memory device, first data and second data are buffered and outputted to a first output node and a second output node, respectively, in a normal mode. In a test mode, the first data is buffered through a first transmission line and a second transmission line and outputted to the first output node and the second output node in response to at least one control signal. Also, in the test mode, the second data is buffered through the first transmission line and the second transmission line and outputted to the first output node and the second output node in response to the at least one control signal. Accordingly, test time may be reduced, and variations of operation characteristics caused by merging the data pins may also be reduced.

公开(公告)号：US6026038A

公开(公告)日：2000-02-15

申请号：US935613

申请日：1997-09-23

Applicant: Soo-In Cho ,  Jong-Hyun Choi

Inventor： Soo-In Cho ,  Jong-Hyun Choi

IPC: G01R31/26 ,  G01R31/28 ,  G11C7/00 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G11C29/025 ,  G11C29/006 ,  G11C29/02 ,  G11C29/50 ,  G11C11/401

Abstract: A wafer burn-in test circuit of a semiconductor memory device having a plurality of memory cells arranged in a row/column matrix, is provided, including: a sub word line driver connected to first and second word line groups each connected to true cells and complement cells forming the memory cells, and responding to a predecoded low address; and first and second power lines respectively supplying power to the corresponding first and second power line groups by a switching operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test operation.

Abstract translation: 提供了具有以行/列矩阵排列的多个存储单元的半导体存储器件的晶片老化测试电路，包括：连接到每个连接到真实单元的第一和第二字线组的子字线驱动器，以及 形成存储器单元的补码单元，以及对预解码的低地址的响应; 以及分别通过子字线驱动器的切换操作向对应的第一和第二电力线组提供电力的第一和第二电力线，其中在正常操作期间将地电源施加到第一和第二电力线，并且 接地电源和升压电源在晶片老化测试操作期间交替施加到第一和第二电源线。