公开(公告)号：US20080036016A1

公开(公告)日：2008-02-14

申请号：US11871876

申请日：2007-10-12

Applicant: Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

Inventor： Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

IPC: H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823481

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract translation: 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

公开(公告)号：US20130043519A1

公开(公告)日：2013-02-21

申请号：US13589339

申请日：2012-08-20

Applicant: Joon-seok Moon ,  Jae-rok Kahng ,  Jin-woo Lee ,  Sung-sam Lee ,  Dong-soo Woo ,  Kyoung-ho Jung ,  Jung-kyu Jung

Inventor： Joon-seok Moon ,  Jae-rok Kahng ,  Jin-woo Lee ,  Sung-sam Lee ,  Dong-soo Woo ,  Kyoung-ho Jung ,  Jung-kyu Jung

IPC: H01L29/78

CPC classification number: H01L29/4236 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/42368

Abstract: A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench.

Abstract translation: 一种器件包括半导体衬底和衬在衬底的有源区中的沟槽的栅极绝缘膜。 栅极电极图案凹陷在栅极绝缘膜上的沟槽中，并且具有不均匀高度的上表面。 电介质图案可以设置在沟槽中的栅电极图案上。

公开(公告)号：US20110183482A1

公开(公告)日：2011-07-28

申请号：US13015838

申请日：2011-01-28

Applicant: Sung-Sam LEE ,  Min-Hee CHO

Inventor： Sung-Sam LEE ,  Min-Hee CHO

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/78

Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.

Abstract translation: 公开了晶体管和晶体管的制造方法。 晶体管设置在由隔离区域限定的衬底的有源区域中，并且包括栅极电极和相关的源极/漏极区域。 隔离区域包括上部隔离区域和下部隔离区域，其中上部隔离区域形成有具有至少部分至少部分为正形状的侧壁。

公开(公告)号：US20070108516A1

公开(公告)日：2007-05-17

申请号：US11552359

申请日：2006-10-24

Applicant: Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

Inventor： Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

IPC: H01L29/94

CPC classification number: H01L21/823437 ,  H01L21/823481

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract translation: 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

公开(公告)号：US06532239B1

公开(公告)日：2003-03-11

申请号：US09206327

申请日：1998-12-08

Applicant: Heon Yong Shim ,  Sung Sam Lee ,  June Man Kim

Inventor： Heon Yong Shim ,  Sung Sam Lee ,  June Man Kim

IPC: H04L1254

CPC classification number: H04Q11/04 ,  H04Q2213/13099 ,  H04Q2213/13103 ,  H04Q2213/13104 ,  H04Q2213/13292 ,  H04Q2213/13299

Abstract: A transmission/reception concurrent matching apparatus for a multiple of TDM channels and a method thereof, wherein in matching the TDM channels, upon data transmission, a signal Serial Communication Controller(SCC) stores data to transmit per each data channel into a multiple of First-in First-out buffers(FIFOs) and transmits in order the data from each FIFO by one byte through a TDM bus, and upon data reception, stores the received data through the TDM bus into each FIFO and processes the data from each FIFO by reading out the data in order. As the number of SCC is reduced, the cost to process the data is saved.

Abstract translation: 一种用于多个TDM信道的发送/接收并发匹配装置及其方法，其中，在匹配TDM信道时，在数据传输时，信号串行通信控制器（SCC）将每个数据信道传输的数据存储为第一 - 先出缓冲器（FIFO），并通过TDM总线将来自每个FIFO的数据按顺序传输一个字节，并且在数据接收时，通过TDM总线将接收到的数据存储到每个FIFO中，并通过 按顺序读出数据。 随着SCC数量的减少，数据的处理成本也得到了节省。

公开(公告)号：US08329539B2

公开(公告)日：2012-12-11

申请号：US11429890

申请日：2006-05-08

Applicant: Dae-Won Ha ,  Kong-Soo Lee ,  Sung-Sam Lee ,  Sang-Hyun Lee ,  Min-Young Shim

Inventor： Dae-Won Ha ,  Kong-Soo Lee ,  Sung-Sam Lee ,  Sang-Hyun Lee ,  Min-Young Shim

IPC: H01L21/336 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66628 ,  H01L29/7834

Abstract: In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.

Abstract translation: 在具有凹陷栅电极的半导体器件及其制造方法中，通过蚀刻半导体衬底在半导体衬底中形成沟槽。 在半导体衬底上形成填充沟槽的第一半导体层。 第二半导体层形成在第一半导体层上，第二半导体层的杂质浓度低于第一半导体层。

公开(公告)号：US08133786B2

公开(公告)日：2012-03-13

申请号：US13015838

申请日：2011-01-28

Applicant: Sung-Sam Lee ,  Min-Hee Cho

Inventor： Sung-Sam Lee ,  Min-Hee Cho

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/78

Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.

Abstract translation: 公开了晶体管和晶体管的制造方法。 晶体管设置在由隔离区域限定的衬底的有源区域中，并且包括栅极电极和相关的源极/漏极区域。 隔离区域包括上部隔离区域和下部隔离区域，其中上部隔离区域形成有具有至少部分至少部分为正形状的侧壁。

公开(公告)号：US20110053327A1

公开(公告)日：2011-03-03

申请号：US12861247

申请日：2010-08-23

Applicant: Jun-Ho YOON ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

Inventor： Jun-Ho YOON ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

IPC: H01L21/336 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02238 ,  H01L21/3065 ,  H01L29/66621

Abstract: Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

Abstract translation: 示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。 该方法包括形成在衬底中限定有源区的场区域。 有源区域在衬底中沿第一方向延伸。 所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及 通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍 牺牲氧化层。

公开(公告)号：US20100019302A1

公开(公告)日：2010-01-28

申请号：US12508305

申请日：2009-07-23

Applicant: Sung-Sam Lee ,  Joon-Seok Moon ,  Young-Ju Choi

Inventor： Sung-Sam Lee ,  Joon-Seok Moon ,  Young-Ju Choi

IPC: H01L27/10 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L21/823437 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/65

Abstract: In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.

Abstract translation: 在半导体器件及其制造方法中，通过器件隔离层将衬底限定为有源区域和非有源区域，并且在有源区域上形成凹部。 栅极电极包括在内侧壁和凹部的底部上的栅极绝缘层，栅极绝缘层上的下部电极和凹部中的下部电极上的内部间隔物，以及位于 内部间隔件并连接到下部电极。 源极和漏极杂质区形成在与上电极相邻的衬底的有源区的表面部分处。 因此，源极和漏极杂质区域如桥接在衬底的凹陷部分中的内部间隔物电绝缘，从而充分防止栅电极处的栅极引起的漏极泄漏（GIDL）。

公开(公告)号：US07622778B2

公开(公告)日：2009-11-24

申请号：US11383141

申请日：2006-05-12

Applicant: Sung-Sam Lee ,  Gyo-Young Jin ,  Yun-Gi Kim

Inventor： Sung-Sam Lee ,  Gyo-Young Jin ,  Yun-Gi Kim

IPC: H01L23/62

CPC classification number: H01L21/76232

Abstract: In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

Abstract translation: 在一个实施例中，半导体器件具有由形成在STI沟槽内部的隔离层限定的有源区，该隔离层包括上沟槽和下沟槽，所述上沟槽和下沟槽在所述上沟槽下方具有基本弯曲的横截面轮廓，使得所述下沟槽处于连通状态 与上沟槽。 由于上沟槽具有以正斜率渐缩的侧壁，因此当用绝缘层填充上沟槽时，可以获得良好的间隙填充性能。 通过在下沟槽中形成空隙，隔离层底部的介电常数低于氧化物层的介电常数，从而提高隔离性能。 隔离层包括仅在上沟槽内形成的第一绝缘层，并且以间隔物的形式覆盖上沟槽的内壁。