公开(公告)号：US06613595B2

公开(公告)日：2003-09-02

申请号：US10058672

申请日：2002-01-28

申请人： Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L2166

CPC分类号： H01L22/32 ,  G01R31/31702 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5002 ,  H01L27/115

摘要： A method is used for testing a tunneling oxide layer of a flash memory. The method includes providing a test device. The test device includes a diffusion region, a floating gate electrode above the diffusion region, and a tunneling oxide layer disposed between the diffusion region and the floating gate electrode. Multiple contacts are disposed over the periphery of the floating gate but not over the diffusion region. Multiple contacts are disposed over the diffusion region. A first voltage is applied to the floating-gate contacts and A second voltage is applied on to the diffusion-region contacts.

摘要翻译： 一种方法用于测试闪存的隧道氧化层。 该方法包括提供测试装置。 测试装置包括扩散区域，扩散区域上方的浮置栅极电极和设置在扩散区域和浮置栅极电极之间的隧道氧化物层。 多个触点设置在浮动栅极的周边上，但不在扩散区域的上方。 多个触点设置在扩散区域上。 第一电压施加到浮栅触点，第二电压施加到扩散区触点。

公开(公告)号：US06455376B1

公开(公告)日：2002-09-24

申请号：US09874455

申请日：2001-06-05

申请人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory is disclosed. The method begins a stacked gate on the substrate. A shallow junction doping is performed on a substrate having a stacked gate already formed thereon, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.

摘要翻译： 公开了一种制造闪速存储器的方法。 该方法在衬底上开始堆叠栅极。 在其上已经形成有堆叠栅极的衬底上执行浅结掺杂，其中堆叠的栅极用作掩模，以便在与栅极的两侧相邻的衬底中形成浅结掺杂区域。 掩模层形成在衬底上以覆盖堆叠栅极的顶表面和侧壁，同时暴露浅结掺杂区域的部分。 在掩模层用作掩模的情况下，在衬底上进行深结掺杂以在衬底中邻近掩模层的两侧形成深结掺杂区域。 在去除掩模层之后，执行热处理以形成具有浅结掺杂区域和深掺杂区域的源极/漏极区域。

公开(公告)号：US07173849B2

公开(公告)日：2007-02-06

申请号：US11198684

申请日：2005-08-04

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C16/02

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

摘要翻译： 多级闪存的编程方法包括拍摄每次逐步向多级闪速存储器的门逐渐增加的编程电压，并且随后，拍摄向下减小的编程验证电压， 在最后一个程序验证电压被拍摄之后，在多级闪存中高电平并在多级闪存中拍摄附加的编程电压。 多级闪速存储器的擦除方法包括拍摄每次逐步向下逐渐减小到多级闪存的门的擦除电压，随后，拍摄向上增加的擦除验证电压以擦除多级闪存， 在最后擦除验证电压被拍摄之后，多级闪存中的电平和多级闪存中的附加电压。

公开(公告)号：US06919607B2

公开(公告)日：2005-07-19

申请号：US10142697

申请日：2002-05-08

申请人： Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L29/78

CPC分类号： H01L27/11253 ,  H01L27/112 ,  H01L27/11266

摘要： A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.

摘要翻译： 提供2位掩模ROM器件的结构及其制造方法。 存储器结构包括衬底，栅极结构，2位编码注入区，间隔区，埋漏区，隔离结构和字线。 栅极结构设置在衬底上，而编码注入区域位于栅极结构侧面的衬底中。 此外，至少一个间隔物布置在栅极结构的侧面旁边，并且掩埋漏极区域设置在衬垫旁边的衬垫旁边。 此外，掩埋漏极区域和编码注入区域还包括其间的缓冲区域。 此外，绝缘结构布置在衬底上方，在掩埋漏极区域之上，而字留置被设置在栅极结构上。

公开(公告)号：US06649971B1

公开(公告)日：2003-11-18

申请号：US10064905

申请日：2002-08-28

申请人： Yen-Hung Yeh ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Yen-Hung Yeh ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L29788

CPC分类号： H01L29/7923

摘要： A NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.

摘要翻译： 描述了用于降低第二位效应的NROM单元。 本发明的NORM单元由衬底，设置在衬底上的氧化硅/氮化硅/氧化硅（ONO）层，设置在氧化硅/氮化硅/氧化硅层上的栅极，源/漏区 配置在栅极旁边的衬底中，以及配置在源极/漏极区域和栅极旁边的ONO层之间的浅阱掺杂区域。 浅阱掺杂区域的深度足够小，以防止对流向源极/漏极区域的电流的干扰。

公开(公告)号：US06531361B1

公开(公告)日：2003-03-11

申请号：US10142720

申请日：2002-05-08

申请人： Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： A fabrication method for a memory device is described. The method includes sequentially forming a pad oxide layer and a mask layer on a substrate, wherein the mask layer exposes a portion of the pad oxide layer. Thereafter, an ion implantation process is conducted to form a buried bit line in the substrate that is not covered by the mask layer. A raised bit line is then formed on the pad oxide layer above the buried bit line. The mask layer and the pad oxide layer are then removed, followed by forming a conformal gate oxide layer on the surface of the substrate and the raised bit line. A word line is further formed on the gate oxide layer.

摘要翻译： 描述了一种用于存储器件的制造方法。 该方法包括在衬底上顺序地形成衬垫氧化物层和掩模层，其中掩模层暴露衬垫氧化物层的一部分。 此后，进行离子注入工艺以在衬底中形成未被掩模层覆盖的掩埋位线。 然后在掩埋位线上方的焊盘氧化物层上形成隆起的位线。 然后去除掩模层和焊盘氧化物层，随后在衬底的表面和凸起的位线上形成共形栅极氧化物层。 在栅极氧化层上进一步形成字线。

公开(公告)号：US06514807B1

公开(公告)日：2003-02-04

申请号：US09955779

申请日：2001-09-18

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Hung-Sui Lin ,  Shih-Keng Cho ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Hung-Sui Lin ,  Shih-Keng Cho ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11293 ,  H01L27/105

摘要： The present invention provides a method for fabricating a semiconductor device that can be applied in system on chip (SOC), comprising: providing a substrate with a memory cell region and a peripheral circuit region; forming a plurality of bit-lines in the memory cell region; forming a first and a second dielectric layers respectively in the memory cell region and the peripheral circuit region; and forming a plurality of gates. Next, a blanket ion implantation step is performed to form a plurality of P type LDDs in the substrate besides the gates in a PMOS device region within the peripheral circuit region, without forming an anti-punch through region in the substrate of the memory cell region. Afterwards, a plurality of spacers are formed, connected to one another. An ion implantation step is performed to form a plurality of P type source/drain regions.

摘要翻译： 本发明提供一种可应用于片上系统（SOC）的半导体器件的制造方法，包括：向衬底提供存储单元区域和外围电路区域; 在所述存储单元区域中形成多个位线; 在所述存储单元区域和所述外围电路区域中分别形成第一和第二电介质层; 并形成多个门。 接下来，进行覆盖离子注入步骤，以在外围电路区域中的PMOS器件区域中的栅极之外的衬底中形成多个P型LDD，而不在存储单元区域的衬底中形成抗穿通区域 。 之后，形成多个间隔件，彼此连接。 执行离子注入步骤以形成多个P型源极/漏极区域。

公开(公告)号：US06444523B1

公开(公告)日：2002-09-03

申请号：US09860422

申请日：2001-05-18

申请人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Wen-Jer Tsai ,  Samuel Pan

发明人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Wen-Jer Tsai ,  Samuel Pan

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A fabrication method for a memory device with a floating gate is provided. A substrate is provided. A channel doping step is performed on the substrate, wherein the actual threshold voltage of the subsequently formed memory device becomes greater than the preset threshold voltage. A stack gate and source/drain regions are then sequentially formed on the substrate to complete the formation of the memory device. The drain-turn-on leakage is prevented by an increase of the actual threshold voltage.

摘要翻译： 提供一种具有浮动栅极的存储器件的制造方法。 提供基板。 在衬底上执行沟道掺杂步骤，其中随后形成的存储器件的实际阈值电压变得大于预设阈值电压。 然后在衬底上顺序地形成堆叠栅极和源极/漏极区，以完成存储器件的形成。 通过实际阈值电压的增加来防止漏极导通泄漏。

公开(公告)号：US07969699B2

公开(公告)日：2011-06-28

申请号：US12186400

申请日：2008-08-05

申请人： Tso-Hung Fan ,  Kuo-Ji Chen

发明人： Tso-Hung Fan ,  Kuo-Ji Chen

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： This invention discloses a trigger circuit for an electrostatic discharge (ESD) protection device, the ESD protection device being turned on during an ESD event and being turned off during a normal operation, the trigger circuit comprises a voltage sensing circuit coupled to a bonding pad, the voltage sensing circuit being configured to produce a first predetermined voltage during a ESD event, and to produce a second predetermined voltage complimentary to the first predetermined voltage during a normal operation, and a voltage converting circuit having a positive feedback circuit and coupled between the voltage sensing circuit and the ESD protection device for converting the first predetermined voltage to a third predetermined voltage for turning on the ESD protection device, and for converting the second predetermined voltage to a fourth predetermined voltage for turning off the ESD protection device.

摘要翻译： 本发明公开了一种用于静电放电（ESD）保护装置的触发电路，ESD保护装置在ESD事件期间被接通并且在正常操作期间被断开，触发电路包括耦合到接合焊盘的电压感测电路， 电压感测电路被配置为在ESD事件期间产生第一预定电压，并且在正常操作期间产生与第一预定电压互补的第二预定电压，以及电压转换电路，具有正反馈电路并耦合在电压 感测电路和用于将第一预定电压转换为用于接通ESD保护装置的第三预定电压的ESD保护装置，以及用于将第二预定电压转换为用于关闭ESD保护装置的第四预定电压。

公开(公告)号：US20070159893A1

公开(公告)日：2007-07-12

申请号：US11616770

申请日：2006-12-27

申请人： TSO-HUNG FAN ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： TSO-HUNG FAN ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

摘要翻译： 多级闪存的编程方法包括拍摄每次逐步向多级闪速存储器的门逐渐增加的编程电压，并且随后，拍摄向下减小的编程验证电压， 在最后一个程序验证电压被拍摄之后，在多级闪存中高电平并在多级闪存中拍摄附加的编程电压。 多级闪速存储器的擦除方法包括拍摄每次逐步向下逐渐减小到多级闪存的门的擦除电压，随后，拍摄向上增加的擦除验证电压以擦除多级闪存， 在最后擦除验证电压被拍摄之后，多级闪存中的电平和多级闪存中的附加电压。