公开(公告)号：US20150070546A1

公开(公告)日：2015-03-12

申请号：US14463743

申请日：2014-08-20

Applicant: Takaaki Negoro ,  Hirofumi Watanabe ,  Katsuhiko Aisu ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano

Inventor： Takaaki Negoro ,  Hirofumi Watanabe ,  Katsuhiko Aisu ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano

IPC: H04N5/355 ,  H04N5/378 ,  H04N5/3745 ,  H01L27/148 ,  H01L27/146

CPC classification number: H04N5/3559 ,  H01L27/14612 ,  H01L27/14638 ,  H01L27/14681 ,  H01L27/148 ,  H04N5/35509 ,  H04N5/3745 ,  H04N5/37457 ,  H04N5/378 ,  H04N5/772 ,  H04N5/907

Abstract: An imaging device includes at least one pixel having a phototransistor which converts light energy into signal charge and varies an amplification factor relative to the intensity of the received light energy, wherein the signal charge of the phototransistor is read out while receiving the light energy with the phototransistor for each pixel.

Abstract translation: 一种成像装置包括至少一个具有光电晶体管的像素，该光电晶体管将光能转换为信号电荷，并相对于所接收的光能的强度改变放大系数，其中光电晶体管的信号电荷在接收光能时读出， 光电晶体管为每个像素。

公开(公告)号：US08878599B2

公开(公告)日：2014-11-04

申请号：US13196983

申请日：2011-08-03

Applicant: Takaaki Negoro

Inventor： Takaaki Negoro

IPC: G06F1/00 ,  G06F3/16 ,  G06F1/28 ,  H01L27/088 ,  H01L27/092 ,  G06F1/30 ,  H01L27/12

CPC classification number: H01L27/0883 ,  G06F1/28 ,  G06F1/30 ,  H01L27/092 ,  H01L27/1203

Abstract: A semiconductor integrated circuit device includes a power-supply terminal to which a power-supply voltage is input; and multiple MOS transistors including an Nch deplete mode MOS transistor functioning as a current source and at least one Pch enhancement mode MOS transistor formed on a silicon-on-insulator substrate including a silicon substrate, a buried-oxide film, and a silicon activate layer, each of the multiple MOS transistors dimensioned so that a bottom of a source diffusion layer and a bottom of a drain diffusion layer reach the buried-oxide film, the at least one Pch enhancement mode MOS transistor being connected to the supply terminal through the Nch depletion mode MOS transistor. The Nch depletion mode MOS transistor has electrical characteristics such that a source voltage thereof is higher than a silicon substrate voltage thereof and a saturation current of the Nch depletion mode MOS transistor is decreased.

Abstract translation: 半导体集成电路装置包括输入电源电压的电源端子; 以及多个MOS晶体管，其包括用作电流源的Nch耗尽型MOS晶体管和形成在包括硅衬底，掩埋氧化膜和硅激活层的绝缘体上硅衬底上的至少一个Pch增强模式MOS晶体管 所述多个MOS晶体管的每一个尺寸使得源极扩散层的底部和漏极扩散层的底部到达掩埋氧化物膜，所述至少一个Pch增强模式MOS晶体管通过Nch连接到所述电源端子 耗尽型MOS晶体管。 N沟道耗尽型MOS晶体管具有使得其源极电压高于其硅衬底电压的电特性，并且Nch耗尽型MOS晶体管的饱和电流降低。

公开(公告)号：US07646242B2

公开(公告)日：2010-01-12

申请号：US12144852

申请日：2008-06-24

Applicant: Takaaki Negoro

Inventor： Takaaki Negoro

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/345 ,  H03F2203/45636

Abstract: A disclosed operational amplifier circuit with a multi-stage amplifier configuration provides fast-response and high withstand-voltage characteristics without using high withstand-voltage transistors as output transistors in its amplifying stages. The output voltage range of a differential amplifier circuit in a first stage is limited by voltage clamping based on a reverse withstand voltage of a bipolar diode. The output voltage range of an amplifier circuit in a second stage is limited by voltage clamping based on a reverse withstand voltage of another bipolar diode. A constant voltage circuit and an apparatus including such an operational amplifier circuit are also disclosed.

Abstract translation: 具有多级放大器配置的公开的运算放大器电路提供快速响应和高耐压特性，而不需要在其放大级中使用高耐压晶体管作为输出晶体管。 第一级差分放大器电路的输出电压范围受到基于双极型二极管的反向耐受电压的钳位限制。 第二级放大器电路的输出电压范围受到基于另一双极二极管的反向耐受电压的钳位限制。 还公开了一种恒压电路和包括这种运算放大器电路的装置。

公开(公告)号：US20060027864A1

公开(公告)日：2006-02-09

申请号：US11244050

申请日：2005-10-06

Applicant: Takaaki Negoro ,  Keiji Fujimoto

Inventor： Takaaki Negoro ,  Keiji Fujimoto

IPC: H01L29/76

CPC classification number: H01L29/7816 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7801 ,  H01L29/7835

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d. Since the source 11s, well region 23, and drain region 24 are respectively self-aligned to the gate electrode 11g, resultant transistor characteristics are stabilized, and the decrease in the on resistance and improved drain threshold voltages can be achieved. Also disclosed herein are bipolar transistors with LDMOS structures, which are capable of obviating the breakdown of gate dielectric layers even at high applied voltage and achieving improved stability in transistor characteristics.

Abstract translation: 公开了具有LDMOS结构的LDMOS晶体管和双极晶体管，用于在高耐压设备应用中的适用。 LDMOS晶体管包括形成在P型衬底1中的漏极阱区21，并且在空间上分离的漏极阱区21是杂质浓度大于漏极区21的杂质浓度的沟道阱区23和中等浓度漏极区24 ，其通过热处理同时形成具有大的扩散深度。 源极11s形成在沟道阱区23中，而漏极11d形成在漏极区24中，杂质浓度大于漏极区24的杂质浓度。 此外，在阱区上形成栅电极11g，覆盖部分重叠的部分与阱区23和漏区24并与漏11d分离。 由于源极11s，阱区23和漏极区24分别与栅极11g自对准，所以晶体管的特性稳定，并且可以实现导通电阻的降低和漏极阈值电压的改善。 本文还公开了具有LDMOS结构的双极型晶体管，其即使在高施加电压下也能够消除栅极电介质层的击穿，并且实现晶体管特性的改善的稳定性。

公开(公告)号：US06911694B2

公开(公告)日：2005-06-28

申请号：US10179371

申请日：2002-06-26

Applicant: Takaaki Negoro ,  Keiji Fujimoto

Inventor： Takaaki Negoro ,  Keiji Fujimoto

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/732 ,  H01L29/735 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7816 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7801 ,  H01L29/7835

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d. Since the source 11s, well region 23, and drain region 24 are respectively self-aligned to the gate electrode 11g, resultant transistor characteristics are stabilized, and the decrease in the on resistance and improved drain threshold voltages can be achieved. Also disclosed herein are bipolar transistors with LDMOS structures, which are capable of obviating the breakdown of gate dielectric layers even at high applied voltage and achieving improved stability in transistor characteristics.

公开(公告)号：US10298869B2

公开(公告)日：2019-05-21

申请号：US15187957

申请日：2016-06-21

Applicant: Katsuhiko Aisu ,  Yasukazu Nakatani ,  Kazuhiro Yoneda ,  Takaaki Negoro ,  Yoshinori Ueda ,  Katsuyuki Sakurano

Inventor： Katsuhiko Aisu ,  Yasukazu Nakatani ,  Kazuhiro Yoneda ,  Takaaki Negoro ,  Yoshinori Ueda ,  Katsuyuki Sakurano

IPC: H01L31/11 ,  H04N5/378 ,  H04N5/363 ,  H04N5/374 ,  H01L27/146 ,  H04N5/225

Abstract: A photoelectric conversion device includes a photoelectric conversion unit which includes a phototransistor having a collector region, an emitter region, and a base region to generate an output current according to an intensity of incident light to the phototransistor, and a base potential setting unit which is configured to set up a base potential of the phototransistor so that the output current from the photoelectric conversion unit is equal to a predetermined current value.

公开(公告)号：US09508871B2

公开(公告)日：2016-11-29

申请号：US14847567

申请日：2015-09-08

Applicant: Katsuyuki Sakurano ,  Takaaki Negoro ,  Yoshinori Ueda ,  Kazuhiro Yoneda ,  Katsuhiko Aisu ,  Yasukazu Nakatani ,  Hirofumi Watanabe

Inventor： Katsuyuki Sakurano ,  Takaaki Negoro ,  Yoshinori Ueda ,  Kazuhiro Yoneda ,  Katsuhiko Aisu ,  Yasukazu Nakatani ,  Hirofumi Watanabe

IPC: H01L29/86 ,  H01L27/146 ,  H01L29/868 ,  H01L29/866

CPC classification number: H01L29/868 ,  H01L27/14603 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14643 ,  H01L29/866

Abstract: A solid-state image sensing device is provided including a first semi-conducting layer of first conductivity, a second semi-conducting layer of first conductivity disposed on the first semi-conducting layer, a semiconductor region of second conductivity different from the first conductivity disposed in the second semi-conducting layer, a deep trench configured to isolate a plurality of neighboring pixels from each other, and an electrode implanted into the deep trench, where the semiconductor region of second conductivity, the second semi-conducting layer, and the first semi-conducting layer are disposed in that order from a proximal side to a distal side, the second semi-conducting layer is split by the deep trench into sections that correspond to the pixels, an impurity concentration of first conductivity of the first semi-conducting layer is higher than an impurity concentration of first conductivity of the second semi-conducting layer, and the deep trench contacts the first semi-conducting layer.

Abstract translation: 提供一种固态图像感测装置，包括：第一导电性的第一半导体层，设置在第一半导电层上的第一导电性的第二半导体层，与第一导电性不同的第二导电性半导体区域 在第二半导电层中，深沟槽被配置为将多个相邻像素彼此隔离，以及注入到深沟槽中的电极，其中第二导电层的半导体区域，第二半导体层和第一半导体层 半导体层从近侧到远侧按顺序设置，第二半导体层被深沟槽分成与像素对应的部分，第一半导电层的第一导电性的杂质浓度 层比第二半导体层的第一导电性的杂质浓度高，并且深沟槽接触第一半导体层 制作层。

公开(公告)号：US09472584B2

公开(公告)日：2016-10-18

申请号：US14604825

申请日：2015-01-26

Applicant: Takaaki Negoro ,  Yoshihiko Miki ,  Katsuyuki Sakurano ,  Keiji Tsuda ,  Hirofumi Watanabe

Inventor： Takaaki Negoro ,  Yoshihiko Miki ,  Katsuyuki Sakurano ,  Keiji Tsuda ,  Hirofumi Watanabe

IPC: H01L31/101 ,  H01L27/144 ,  H01L31/02 ,  H01L27/146

CPC classification number: H01L27/1443 ,  H01L27/14681 ,  H01L31/02019

Abstract: A phototransistor includes a first emitter region, a first base region having at least a portion exposed to a light-receiving side, and a first collector region in this order from the light-receiving side in a depth direction. The first collector region includes a second collector region and a third collector region that is in contact with a downstream side of the second collector region in the depth direction and has a resistance lower than that of the second collector region. The phototransistor further includes a first region that is spaced away from the first base region at an outer side of the first base region on a light-receiving side surface thereof, the first region having a conductivity type opposite to that of the first collector region.

Abstract translation: 光电晶体管包括第一发射极区域，具有从光接收侧暴露的至少一部分的第一基极区域和沿着深度方向的光接收侧的顺序的第一集电极区域。 第一集电极区域包括与深度方向上的第二集电极区域的下游侧接触的第二集电极区域和第三集电极区域，并且具有比第二集电极区域的电阻低的电阻。 光电晶体管还包括在其受光侧表面上的第一基区的外侧与第一基区间隔开的第一区域，第一区域具有与第一集电区域相反的导电类型。

公开(公告)号：US20150214413A1

公开(公告)日：2015-07-30

申请号：US14604825

申请日：2015-01-26

Applicant: Takaaki NEGORO ,  Yoshihiko MIKI ,  Katsuyuki SAKURANO ,  Keiji TSUDA ,  Hirofumi WATANABE

Inventor： Takaaki NEGORO ,  Yoshihiko MIKI ,  Katsuyuki SAKURANO ,  Keiji TSUDA ,  Hirofumi WATANABE

IPC: H01L31/11 ,  H01L27/144 ,  H01L27/082

CPC classification number: H01L27/1443 ,  H01L27/14681 ,  H01L31/02019

Abstract: A phototransistor includes a first emitter region, a first base region having at least a portion exposed to a light-receiving side, and a first collector region in this order from the light-receiving side in a depth direction. The first collector region includes a second collector region and a third collector region that is in contact with a downstream side of the second collector region in the depth direction and has a resistance lower than that of the second collector region. The phototransistor further includes a first region that is spaced away from the first base region at an outer side of the first base region on a light-receiving side surface thereof, the first region having a conductivity type opposite to that of the first collector region.

Abstract translation: 光电晶体管包括第一发射极区域，具有从光接收侧暴露的至少一部分的第一基极区域和沿着深度方向的光接收侧的顺序的第一集电极区域。 第一集电极区域包括与深度方向上的第二集电极区域的下游侧接触的第二集电极区域和第三集电极区域，并且具有比第二集电极区域的电阻低的电阻。 光电晶体管还包括在其受光侧表面上的第一基区的外侧与第一基区间隔开的第一区域，第一区域具有与第一集电区域相反的导电类型。

公开(公告)号：US20140367550A1

公开(公告)日：2014-12-18

申请号：US14305821

申请日：2014-06-16

Applicant: Katsuhiko AISU ,  Takaaki Negoro ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano ,  Hirobumi Watanabe

Inventor： Katsuhiko AISU ,  Takaaki Negoro ,  Kazuhiro Yoneda ,  Katsuyuki Sakurano ,  Hirobumi Watanabe

IPC: H01L27/144

CPC classification number: H01L27/144 ,  H01L27/14609 ,  H04N5/359 ,  H04N5/374 ,  H04N5/3745

Abstract: A photoelectric conversion device includes a first output line, a second output line; and a photoelectric conversion cell. The photoelectric conversion cell further includes, a photoelectric conversion element configured to generate an output current corresponding to an intensity of incident light, a first switch element configured to transmit the first output current to the first output line according to a first control signal, and a second switch element configured to transmit the second output current to second output line according to a second control signal. As a result, the photoelectric conversion device can be provided to generate rapidly the image data with wide dynamic range without the need for complex control outside of the photoelectric conversion device.

Abstract translation: 光电转换装置包括第一输出线，第二输出线， 和光电转换单元。 光电转换单元还包括：光电转换元件，被配置为产生与入射光强度相对应的输出电流;第一开关元件，被配置为根据第一控制信号将第一输出电流传输到第一输出线;以及 第二开关元件，被配置为根据第二控制信号将第二输出电流传输到第二输出线。 结果，可以提供光电转换装置以快速生成具有宽动态范围的图像数据，而不需要光电转换装置外部的复杂控制。