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    Half-rate DFE with duplicate path for high data-rate operation
    11.
    发明授权
    Half-rate DFE with duplicate path for high data-rate operation 有权
    具有高数据速率操作的重复路径的半速率DFE

    公开(公告)号：US07782935B1

    公开(公告)日：2010-08-24

    申请号：US11514490

    申请日：2006-08-31

    Applicant: Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

    Inventor： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Tin H. Lai

    IPC: H03H7/30

    CPC classification number: H03H11/26 ,  H04L25/03878 ,  H04L2025/0349

    Abstract: Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

    Abstract translation: 提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。 半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。 可以使用以输入信号数据速率的一半工作的两个延迟链电路。 更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。 多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。 重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。 第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

    Systems and methods for offset cancellation in integrated transceivers
    13.
    发明授权
    Systems and methods for offset cancellation in integrated transceivers 有权
    集成收发器偏移消除的系统和方法

    公开(公告)号：US07586983B1

    公开(公告)日：2009-09-08

    申请号：US11510446

    申请日：2006-08-24

    Applicant: Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    Inventor： Sergey Shumarayev ,  Wilson Wong ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC: H03K5/159 ,  H04B1/10

    CPC classification number: H04L25/03057

    Abstract: In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.

    Abstract translation: 在高速接收机电路（例如，在可编程逻辑器件（PLD）等上）中，使用判决反馈均衡（DFE）电路来至少部分地消除不期望的偏移（例如，从接收机的其他元件）。 输入到接收机的数据被三态化; 然后依次改变每个DFE抽头系数，以找到与接收机输出信号的振荡和非振荡之间的转换相关联的系数值。 以这种方式找到的系数值用于选择试验值。 如果接收机的输出信号在使用这些试验值时不振荡，则从这些（或后续）试验值开始重复该过程，直到最终的试验值确定允许接收器输出信号的振荡。

    Variable-bandwidth loop filter methods and apparatus
    15.
    发明授权
    Variable-bandwidth loop filter methods and apparatus 失效
    可变带宽环路滤波器的方法和装置

    公开(公告)号：US07436228B1

    公开(公告)日：2008-10-14

    申请号：US11317126

    申请日：2005-12-22

    Applicant: Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

    Inventor： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

    IPC: H03K5/00 ,  H03L7/06

    CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/18

    Abstract: Methods and apparatus are provided for varying the bandwidth of a loop filter in a loop circuit (e.g., a phase-locked loop circuit). The loop filter can include first and second resistor circuitries coupled to a capacitor. One of the resistor circuitries can be coupled to an output of the loop circuit in response to selection of a mode of operation. The resistor circuitries can each include a plurality of resistors that can be selectively coupled in series to the capacitor or bypassed. In addition, the output of the loop circuit can be coupled to a second capacitor. Either or both of the capacitors can be programmable.

    Abstract translation: 提供了用于改变环路电路（例如，锁相环电路）中的环路滤波器的带宽的方法和装置。 环路滤波器可以包括耦合到电容器的第一和第二电阻器电路。 响应于操作模式的选择，电阻器电路中的一个可以耦合到环路电路的输出。 电阻器电路可以各自包括可以选择性地串联耦合到电容器或绕过的多个电阻器。 此外，环路电路的输出可以耦合到第二电容器。 电容器中的任一个或两个可以是可编程的。

    Modular buffering circuitry for multi-channel transceiver clock and other signals
    17.
    发明授权
    Modular buffering circuitry for multi-channel transceiver clock and other signals 有权
    用于多通道收发器时钟和其他信号的模块化缓冲电路

    公开(公告)号：US07304507B1

    公开(公告)日：2007-12-04

    申请号：US11288496

    申请日：2005-11-28

    Applicant: Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

    Inventor： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

    IPC: H03K19/00

    CPC classification number: H03K19/17736 ,  H03K19/17744

    Abstract: Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.

    Abstract translation: 在集成电路（例如现场可编程门阵列（“FPGA”）上的收发器电路块之间分配诸如参考时钟信号的信号的电路采用双向缓冲器而不是单向缓冲器。 这允许所有缓冲器具有相同的结构，而不管物理位置如何，这有助于使用相同或基本相同的模块构建电路。 相同的方法可以用于在收发器块之间分配其他类型的信号。 例如，该方法可用于分配校准控制信号。

    Equalizer circuitry including both inductor based and non-inductor based equalizer stages
    19.
    发明授权
    Equalizer circuitry including both inductor based and non-inductor based equalizer stages 有权
    均衡器电路包括基于电感和非电感的均衡器级

    公开(公告)号：US08816745B1

    公开(公告)日：2014-08-26

    申请号：US13316361

    申请日：2011-12-09

    Applicant: Sangeeta Raman ,  Tim Tri Hoang

    Inventor： Sangeeta Raman ,  Tim Tri Hoang

    IPC: H03L5/00

    CPC classification number: H04L25/03878 ,  H03K19/018507

    Abstract: An equalizer circuitry that includes both inductor based and non-inductor based equalizer stages is provided. In one implementation, the equalizer circuitry includes a first equalizer circuitry including a first inductor based equalizer stage and a first non-inductor based equalizer stage coupled to the first inductor based equalizer stage. In one implementation, the equalizer circuitry further includes a second equalizer circuitry including a plurality of inductor based equalizer stages, where the plurality of inductor based equalizer stages includes the first inductor based equalizer stage. In one implementation, the first equalizer circuitry further includes a second inductor based equalizer stage coupled to the first inductor based equalizer stage and the first non-inductor based equalize stage.

    Abstract translation: 提供了包括基于电感器和非电感器的均衡器级的均衡器电路。 在一个实现中，均衡器电路包括第一均衡器电路，其包括基于第一电感器的均衡器级和耦合到基于第一电感器的均衡器级的基于非电感器的第一非均衡器级。 在一个实现中，均衡器电路还包括包括多个基于电感器的均衡器级的第二均衡器电路，其中多个基于电感器的均衡器级包括基于第一电感器的均衡器级。 在一个实现中，第一均衡器电路还包括耦合到基于第一电感器的均衡器级和基于非电感器的第一非均衡级的基于第二电感器的均衡器级。

    Technique for providing loopback testing with single stage equalizer
    20.
    发明授权
    Technique for providing loopback testing with single stage equalizer 有权
    提供单级均衡器的环回测试技术

    公开(公告)号：US08705605B1

    公开(公告)日：2014-04-22

    申请号：US13288701

    申请日：2011-11-03

    Applicant: Sangeeta Raman ,  Tim Tri Hoang

    Inventor： Sangeeta Raman ,  Tim Tri Hoang

    IPC: H03K5/159 ,  H03H7/30 ,  H03H7/40

    CPC classification number: H04L1/243 ,  H04B17/14 ,  H04L25/03878 ,  H04W52/0274 ,  Y02D70/00

    Abstract: Devices and methods for serial loopback testing in an integrated circuit (IC) are provided. To implement loopback testing, an equalizer stage of a receiver of the IC is powered down. In addition, the common-mode voltage of the equalizer stage is reduced and/or a bulk node of the equalizer stage is connected to ground. Doing so may reduce the impact of capacitive coupling from the input pins of buffer, thereby improving the quality of the loopback output signal.

    Abstract translation: 提供了集成电路（IC）中串行回送测试的设备和方法。 为了实现环回测试，IC的接收机的均衡器级掉电。 此外，均衡器级的共模电压被减小和/或均衡器级的体积节点连接到地。 这样做可以减少来自缓冲器的输入引脚的电容耦合的影响，从而提高环回输出信号的质量。

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