公开(公告)号：US6156126A

公开(公告)日：2000-12-05

申请号：US484790

申请日：2000-01-18

Applicant: Tung-Po Chen ,  Jih-Wen Chou

Inventor： Tung-Po Chen ,  Jih-Wen Chou

IPC: G03F7/42 ,  H01L21/265 ,  H01L21/306 ,  H01L21/336 ,  B08B3/04

CPC classification number: H01L21/02052 ,  H01L21/26513 ,  H01L29/6659 ,  G03F7/422 ,  Y10S134/902

Abstract: A method for cleaning a silicon wafer. The method includes intentionally exposing the wafer into a volatile solvent with a polarity between about 2 and 4, whereby the wafer is cleaned by the solvent such that the formation of silicon recesses in source/drain extension regions on the silicon wafer can be prevented or avoided.

Abstract translation: 一种清洗硅晶片的方法。 该方法包括将晶片有意地暴露在极性为约2和4之间的挥发性溶剂中，由此通过溶剂清洁晶片，从而可以防止或避免在硅晶片上的源极/漏极延伸区域中形成硅凹槽 。

公开(公告)号：US6153520A

公开(公告)日：2000-11-28

申请号：US258117

申请日：1999-02-24

Applicant: Tung-Po Chen

Inventor： Tung-Po Chen

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44

CPC classification number: H01L21/28518

Abstract: A method to fabricate a salicide layer is described. The method is performed by forming a metal layer on the polysilicon gate and source/drain region and by a chemical vapor deposition using TiCl.sub.4 as a source gas. The metal layer is in situ transformed into a silicide layer in the formation step of the metal layer.

Abstract translation: 描述了制造自对准硅化物层的方法。 该方法通过在多晶硅栅极和源极/漏极区域上形成金属层并且通过使用TiCl 4作为源气体的化学气相沉积来进行。 金属层在金属层的形成步骤中原位转化为硅化物层。

公开(公告)号：US20060281251A1

公开(公告)日：2006-12-14

申请号：US11164332

申请日：2005-11-18

Applicant: Wen-Ji Chen ,  Tung-Po Chen ,  Kai-An Hsueh ,  Sheng-Hone Zheng

Inventor： Wen-Ji Chen ,  Tung-Po Chen ,  Kai-An Hsueh ,  Sheng-Hone Zheng

IPC: H01L21/8242

CPC classification number: H01L27/105 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/11546 ,  Y10S438/981

Abstract: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.

Abstract translation: 提供一种用于制造栅介质层的方法。 提供了分成至少高压电路区域和低电压电路区域的衬底。 在基板上形成用作高电压电路区域中的栅极电介质层的第一介质层。 在第一电介质层上形成掩模层。 将掩模层，第一介电层和衬底图案化以在衬底中形成沟槽。 形成隔离层以填充沟槽。 去除掩模层和隔离层的一部分以露出第一介电层的表面。 去除低电压电路区域的第一电介质层以暴露衬底的表面。 在低电压电路区域的基板上形成厚度小于第一电介质层的第二电介质层。

公开(公告)号：US20060030136A1

公开(公告)日：2006-02-09

申请号：US10905086

申请日：2004-12-14

Applicant: Tung-Po Chen

Inventor： Tung-Po Chen

IPC: H01L21/469

CPC classification number: H01L21/26506 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76232

Abstract: A method of fabrication a gate oxide layer includes providing a substrate and an isolation structure on the substrate so as to isolate an active region. A spacer is formed on the sidewalls of the isolation structure. Using the isolation structure having the spacer as a mask, a dopant is implanted into the substrate for reducing the oxidation rate of the substrate. Thereafter, the spacer and a portion of the isolation structure are removed and an oxidation process is performed to form a gate oxide layer with a uniform thickness over the substrate.

Abstract translation: 制造栅极氧化物层的方法包括在衬底上提供衬底和隔离结构以隔离有源区。 间隔件形成在隔离结构的侧壁上。 使用具有间隔物的隔离结构作为掩模，将掺杂剂注入到衬底中以降低衬底的氧化速率。 此后，去除间隔物和隔离结构的一部分，并进行氧化处理以在衬底上形成均匀厚度的栅极氧化物层。

公开(公告)号：US06426256B1

公开(公告)日：2002-07-30

申请号：US09375518

申请日：1999-08-17

Applicant: Tung-Po Chen

Inventor： Tung-Po Chen

IPC: H01L218242

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L27/10873

Abstract: A method for manufacturing an embedded DRAM with self-aligned borderless contacts is provided. The method comprises providing a substrate having a first device region and a second device region. The first device region comprises a first transistor and the second device region has a second transistor. A silicide block layer is formed over the second device region. An etching stop layer covers all device regions. A mask layer covers the first device region. Then the etching stop layer not covered by the mask layer is removed. A first dielectric material layer is formed on all the device regions and therein a first contact window is on the second device region. A second dielectric material layer is next formed and therein a second contact window is on the second device region. A third dielectric material layer is formed and therein at least a third contact window is coupled to the first transistor of the first device region. A borderless contact is consisted of the contact window coupled to the substrate and a metallic node on the contact window.

Abstract translation: 提供了一种用于制造具有自对准无边界触点的嵌入式DRAM的方法。 该方法包括提供具有第一器件区域和第二器件区域的衬底。 第一器件区域包括第一晶体管，第二器件区域具有第二晶体管。 在第二器件区域上形成硅化物阻挡层。 蚀刻停止层覆盖所有设备区域。 掩模层覆盖第一设备区域。 然后去除未被掩模层覆盖的蚀刻停止层。 第一介电材料层形成在所有器件区域上，其中第一接触窗口位于第二器件区域上。 接下来形成第二电介质材料层，其中第二接触窗口位于第二器件区域上。 形成第三介电材料层，并且其中至少第三接触窗口耦合到第一器件区域的第一晶体管。 无边界接触由耦合到基板的接触窗口和接触窗口上的金属节点组成。

公开(公告)号：US06228730B1

公开(公告)日：2001-05-08

申请号：US09301211

申请日：1999-04-28

Applicant: Tung-Po Chen ,  Jih-Wen Chou

Inventor： Tung-Po Chen ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7834

Abstract: A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

Abstract translation: 一种制造场效应晶体管的方法，其中提供具有栅极的基板。 衬套氧化物层和第一间隔件邻近栅极的侧面形成。 在衬底的栅极的两侧形成外延硅层，而在外延硅层下面的衬底中形成浅源极/漏极（S / D）延伸结。 形成氧化物层和第二间隔物以紧密地连接到第一间隔物并在外延硅层下面形成S / D区。 然后将外延硅层的一部分转变成金属硅化物层，以完成场效应晶体管的工艺。

公开(公告)号：US06225155B1

公开(公告)日：2001-05-01

申请号：US09208602

申请日：1998-12-08

Applicant: Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

Inventor： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

IPC: H01L218234

CPC classification number: H01L27/10894 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/10873

Abstract: In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.

Abstract translation: 在嵌入式动态随机存取存储器中形成硅化物层的方法中，在对源极/漏极区域进行退火处理之后，在衬底上顺序地形成薄氧化物层，氮化硅层和厚氧化物层。 逻辑区域中的栅极和源极/漏极区域上的绝缘层以及存储区域中的栅极。 在上述三个区域上形成硅化物层。 自对准层的形成可以降低三个区域的电阻，提高速度，并且可以避免在存储区域的源极/漏极区域上形成自对准硅化物层。 因此，可以避免电流泄漏。 此外，在源极/漏极区域的退火处理之后进行形成硅化物层的步骤，因此也可以解决多晶硅层中的杂质的热稳定性和相互扩散问题。

公开(公告)号：US06197672B1

公开(公告)日：2001-03-06

申请号：US09208271

申请日：1998-12-08

Applicant: Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

Inventor： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

IPC: H01L213205

CPC classification number: H01L21/28061 ,  H01L29/4941

Abstract: A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.

Abstract translation: 一种形成双重多晶硅栅极的方法。 提供具有隔离结构的衬底，在衬底上沉积多晶硅层（或α-Si层），将N型和P型掺杂剂注入到多晶硅层中以形成具有N- 型门和P型门。 执行退火步骤以恢复多晶硅层的表面晶体结构，在掺杂多晶硅层上沉积氧化物层，并且在氧化物层上形成硅化物层。 硅化物层，氧化物层和多晶硅层被定义为形成多晶硅栅极，在衬底的栅极旁边形成轻掺杂的源极/漏极区域。 在栅极的侧壁上形成间隔物，并且在衬底中的间隔物旁边形成重掺杂的源/漏区。

公开(公告)号：US06177334B1

公开(公告)日：2001-01-23

申请号：US09203024

申请日：1998-12-01

Applicant: Tung-Po Chen ,  Yung-Chang Lin ,  Jacob Chen

Inventor： Tung-Po Chen ,  Yung-Chang Lin ,  Jacob Chen

IPC: H01L2120

CPC classification number: H01L21/02071 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32137 ,  H01L29/6659

Abstract: A manufacturing method is capable of preventing corrosion of a metal oxide semiconductor. The manufacturing method sequentially forms a polysilicon layer, a silicide layer and a top cap layer over a substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the silicide layer. Finally, the substrate is cleaned, and then of a source/drain region having a lightly doped drain structure is formed on each side of the gate.

Abstract translation: 制造方法能够防止金属氧化物半导体的腐蚀。 制造方法在衬底上顺序地形成多晶硅层，硅化物层和顶盖层，然后蚀刻以形成栅极结构。 接下来，进行快速热处理以在硅化物层的暴露的侧壁上形成氧化物层。 最后，清洗衬底，然后在栅极的每一侧形成具有轻掺杂漏极结构的源/漏区。

公开(公告)号：US6010958A

公开(公告)日：2000-01-04

申请号：US907005

申请日：1997-08-06

Applicant: Tung-Po Chen ,  Bing-Chang Wu ,  Hong-Tsz Pan

Inventor： Tung-Po Chen ,  Bing-Chang Wu ,  Hong-Tsz Pan

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/3105 ,  H01L21/76819 ,  Y10S438/937

Abstract: A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.

Abstract translation: 一种在制造金属互连件时改善电介质层的平面化的方法，其中使用快速热处理操作以便在介电层局部平坦化之后固化电介质层的暴露表面。 该方法避免了在预金属蚀刻操作期间对介电层的损坏，因此，防止在随后的钨沉积期间残留的钨变成楔形，从而产生可能导致与金属布线接触的短路的桁条。