公开(公告)号：US20050287814A1

公开(公告)日：2005-12-29

申请号：US11140115

申请日：2005-05-27

Applicant: Yuan-Bang Lee ,  Tzu-Yang Wu ,  Sheug-Liang Pan ,  U. Lin ,  Yu-Chih Lai ,  De-Fang Chen

Inventor： Yuan-Bang Lee ,  Tzu-Yang Wu ,  Sheug-Liang Pan ,  U. Lin ,  Yu-Chih Lai ,  De-Fang Chen

IPC: G03F7/42 ,  H01L21/00 ,  H01L21/26 ,  H01L21/302 ,  H01L21/311 ,  H01L21/324 ,  H01L21/42 ,  H01L21/461 ,  H01L21/477

CPC classification number: G03F7/427 ,  H01L21/31138 ,  H01L21/67069

Abstract: An in-situ method of stripping a layer of resist from a substrate or wafer utilizes pure H2O plasma recipe to substantially prevent charges from accumulating on the substrate or wafer during stripping of the layer of resist.

Abstract translation: 从衬底或晶片剥离抗蚀剂层的原位方法利用纯H 2 O 2等离子体配方，以在剥离抗蚀剂层期间基本上防止电荷积聚在衬底或晶片上。

公开(公告)号：US20050260784A1

公开(公告)日：2005-11-24

申请号：US10978011

申请日：2004-10-29

Applicant: Fei-Yun Chen ,  Wei-Ya Wang ,  Yuh-Hwa Chang ,  Tzu-Yang Wu

Inventor： Fei-Yun Chen ,  Wei-Ya Wang ,  Yuh-Hwa Chang ,  Tzu-Yang Wu

IPC: G02B26/08 ,  H01L21/00

CPC classification number: G02B26/0833

Abstract: An MEMS mirror structure is formed using an etching process that forms sidewall oxide spacers while maintaining the integrity of the oxide layer formed over the reflective layer of the MEMS mirror structure. The discrete mirror structure is formed to include a reflective layer sandwiched between oxide layers and with a protect layer formed over the upper oxide layer. A spacer oxide layer is formed to cover the structure and oxide spacers are formed on sidewalls of the discrete structure using a selective etch process that is terminated when horizontal portions of the spacer oxide layer have cleared to expose the release layer formed below the discrete mirror structure and the protect layer. The superjacent protect layer prevents the spacer oxide etch process from attacking the upper oxide layer and therefore maintains the integrity of the upper oxide layer and the functionality of the mirror structure.

Abstract translation: 使用形成侧壁氧化物间隔物的蚀刻工艺形成MEMS镜结构，同时保持在MEMS镜结构的反射层上形成的氧化物层的完整性。 离散镜结构被形成为包括夹在氧化物层之间的反射层和形成在上氧化物层上的保护层。 形成间隔氧化物层以覆盖该结构，并且使用选择性蚀刻工艺在离散结构的侧壁上形成氧化物间隔物，该选择性蚀刻工艺在间隔氧化物层的水平部分已经清除以暴露形成在离散镜结构下方的释放层时终止 和保护层。 上部保护层防止间隔氧化物蚀刻工艺攻击上部氧化物层，从而保持上部氧化物层的完整性和反射镜结构的功能。

公开(公告)号：US07838386B2

公开(公告)日：2010-11-23

申请号：US12235960

申请日：2008-09-23

Applicant: Ruei-Hung Jang ,  Ya-Wen Lee ,  Tzu-Yang Wu ,  Sheng-Liang Pan ,  Chin-Hsiang Lin ,  Tsai-Sheng Gau

Inventor： Ruei-Hung Jang ,  Ya-Wen Lee ,  Tzu-Yang Wu ,  Sheng-Liang Pan ,  Chin-Hsiang Lin ,  Tsai-Sheng Gau

IPC: H01L21/76 ,  H01L21/00 ,  H01L23/544

CPC classification number: G02B26/0841

Abstract: Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Abstract translation: 公开了一种在透明基板上形成对准标记的方法和系统。 光反射层沉积在晶片的光学透明衬底上。 围绕光学透明基板上的对准标记限定区域。 除了该区域之外，从透明基板的大部分除去光反射层。 另外，公开了一种微电子机械系统装置。 该器件包括光学透明衬底，在光学透明衬底上的至少一个光学部分透明的对准标记，以及附接到光学透明衬底的多个反射元件或成像像素。

公开(公告)号：US07494830B2

公开(公告)日：2009-02-24

申请号：US11697543

申请日：2007-04-06

Applicant: Sheng-Chieh Liu ,  Tzu-Yang Wu ,  Ya-Wen Lee ,  Jeffery Chu ,  Hsueh-Liang Chou ,  Chia-Hung Kao

Inventor： Sheng-Chieh Liu ,  Tzu-Yang Wu ,  Ya-Wen Lee ,  Jeffery Chu ,  Hsueh-Liang Chou ,  Chia-Hung Kao

IPC: H01L23/544

CPC classification number: H01L22/34 ,  B81C1/00603 ,  B81C99/0065 ,  B81C2203/051 ,  G03F7/70633 ,  G03F9/7084 ,  G03F9/7088 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

Abstract translation: 一种用于晶片背面对准覆盖精度的方法包括在晶片的正面上形成掩埋层; 在所述掩埋层上形成导电层并在其中构图第一测试结构和第二测试结构; 在导电层上形成蚀刻停止层; 从背面蚀刻晶片以对第一测试结构执行对准过程; 以及确定与第二测试结构的对准过程的重叠精度。 第一测试结构包括光学游标，第二测试结构包括电测试结构。

公开(公告)号：US20070249137A1

公开(公告)日：2007-10-25

申请号：US11409582

申请日：2006-04-24

Applicant: Sheng-Chieh Liu ,  Chia-Hung Kao ,  Tzu-Yang Wu ,  Sheng-Liang Pan ,  Yuan-Bang Lee

Inventor： Sheng-Chieh Liu ,  Chia-Hung Kao ,  Tzu-Yang Wu ,  Sheng-Liang Pan ,  Yuan-Bang Lee

IPC: H01L21/306 ,  H01L21/76 ,  H01L21/302

CPC classification number: B81C1/00603

Abstract: Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.

Abstract translation: 公开了一种用于晶片背面对准的方法和系统。 在基板的正面上形成零标记。 多个层沉积在基板的正面上。 将晶片的背面朝上翻转，从背面到沉积在基板前侧的蚀刻停止层进行贯通晶片蚀刻。

公开(公告)号：US20080248600A1

公开(公告)日：2008-10-09

申请号：US11697543

申请日：2007-04-06

Applicant: Sheng-Chieh Liu ,  Tzu-Yang Wu ,  Ya-Wen Lee ,  Jeffrey Chu ,  Hsueh-Liang Chou ,  Chia-Hung Kao

Inventor： Sheng-Chieh Liu ,  Tzu-Yang Wu ,  Ya-Wen Lee ,  Jeffrey Chu ,  Hsueh-Liang Chou ,  Chia-Hung Kao

IPC: H01L21/00

CPC classification number: H01L22/34 ,  B81C1/00603 ,  B81C99/0065 ,  B81C2203/051 ,  G03F7/70633 ,  G03F9/7084 ,  G03F9/7088 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

Abstract translation: 一种用于晶片背面对准覆盖精度的方法包括在晶片的正面上形成掩埋层; 在所述掩埋层上形成导电层并在其中构图第一测试结构和第二测试结构; 在导电层上形成蚀刻停止层; 从背面蚀刻晶片，以与第一测试结构进行对准过程; 以及确定与第二测试结构的对准过程的重叠精度。 第一测试结构包括光学游标，第二测试结构包括电测试结构。

公开(公告)号：US20080061030A1

公开(公告)日：2008-03-13

申请号：US11531590

申请日：2006-09-13

Applicant: Sheng-Chieh Liu ,  Tzu-Yang Wu ,  Sheng-Liang Pan ,  Yuan-Bang Lee ,  U. H. Lin

Inventor： Sheng-Chieh Liu ,  Tzu-Yang Wu ,  Sheng-Liang Pan ,  Yuan-Bang Lee ,  U. H. Lin

IPC: C23F1/00

CPC classification number: H01L31/1884 ,  Y02E10/50

Abstract: A method of patterning an indium tin oxide film includes the steps of forming a cap layer over the indium tin oxide film and subjecting exposed areas of the indium tin oxide film to a water plasma.

Abstract translation: 图案化氧化铟锡膜的方法包括以下步骤：在氧化铟锡膜上形成覆盖层，并使铟锡氧化物膜的暴露区域成为水等离子体。

公开(公告)号：US20070177244A1

公开(公告)日：2007-08-02

申请号：US11400974

申请日：2006-04-10

Applicant: Ruei-Hung Jang ,  Ya-Wen Lee ,  Tzu-Yang Wu ,  Sheng-Liang Pan ,  Chin-Hsiang Lin ,  Tsai-Sheng Gau

Inventor： Ruei-Hung Jang ,  Ya-Wen Lee ,  Tzu-Yang Wu ,  Sheng-Liang Pan ,  Chin-Hsiang Lin ,  Tsai-Sheng Gau

IPC: G02B26/00

CPC classification number: G02B26/0841

Abstract: Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Abstract translation: 公开了一种在透明基板上形成对准标记的方法和系统。 光反射层沉积在晶片的光学透明衬底上。 围绕光学透明基板上的对准标记限定区域。 除了该区域之外，从透明基板的大部分除去光反射层。 另外，公开了一种微电子机械系统装置。 该器件包括光学透明衬底，在光学透明衬底上的至少一个光学部分透明的对准标记，以及附接到光学透明衬底的多个反射元件或成像像素。

公开(公告)号：US07183171B2

公开(公告)日：2007-02-27

申请号：US11252328

申请日：2005-10-17

Applicant: Kun-Ming Huang ,  YJ Wang ,  Ying-De Chen ,  Eugene Chu ,  Fu-Hsin Chen ,  Tzu-Yang Wu

Inventor： Kun-Ming Huang ,  YJ Wang ,  Ying-De Chen ,  Eugene Chu ,  Fu-Hsin Chen ,  Tzu-Yang Wu

IPC: H01L21/8242

CPC classification number: H01L28/60

Abstract: A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.

Abstract translation: 公开了一种电容器结构，其具有通常为锥形或阶梯形轮廓以防止或减少介电层击穿。 电容器结构包括第一导电层，至少一个电介质层，其具有设置在第一导电层上的第一区域和设置在至少一个电介质层上的第二导电层。 第二导电层具有小于至少一个电介质层的第一区域的第二区域。 还公开了一种制造电容器结构的方法。