公开(公告)号：US20090186475A1

公开(公告)日：2009-07-23

申请号：US12017065

申请日：2008-01-21

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Yao-Chin Cheng ,  Chi-Sheng Tseng ,  Yu-Ming Lin ,  Shih-Jung Tu ,  Tzyy-Ming Cheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Yao-Chin Cheng ,  Chi-Sheng Tseng ,  Yu-Ming Lin ,  Shih-Jung Tu ,  Tzyy-Ming Cheng

IPC分类号： H01L21/3205

CPC分类号： H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.

摘要翻译： 一种制造MOS晶体管的方法，其中使用三层光致抗蚀剂层来形成具有声音形状和小尺寸的图案化硬掩模层，并且使用图案化的硬掩模层来形成栅极。 此后，通过形成和限定盖层，通过在衬底中的蚀刻形成凹陷。 在凹槽中形成外延层之后去除图案化的硬掩模。 因此，可以避免导致接触桥的常规多晶块问题和STI氧化物损耗问题。

公开(公告)号：US20090166625A1

公开(公告)日：2009-07-02

申请号：US11966734

申请日：2007-12-28

申请人： Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

发明人： Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

摘要翻译： 本发明提供一种形成金属氧化物半导体（MOS）器件的方法及其结构。 该方法至少包括通过第一选择性外延生长工艺形成硅锗层并通过第二选择性外延生长工艺在硅锗层上形成覆盖层的步骤。 因此，可以减轻离子注入引起的不良影响。

公开(公告)号：US07550356B2

公开(公告)日：2009-06-23

申请号：US11164177

申请日：2005-11-14

申请人： Cheng-Tung Huang ,  Chia-Wen Liang ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Cheng-Tung Huang ,  Chia-Wen Liang ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/6653 ,  Y10S438/938

摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.

摘要翻译： 制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底包括栅极，至少间隔物和源极/漏极区域; 执行第一快速热退火（RTA）工艺; 去除间隔物并在栅极和源极/漏极区域的表面上形成高拉伸应力膜; 并进行第二快速热退火处理。

公开(公告)号：US20080242031A1

公开(公告)日：2008-10-02

申请号：US11692609

申请日：2007-03-28

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659

摘要： A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

摘要翻译： 制造p型沟道FET的方法包括在衬底上形成栅极。 然后，执行PAI离子注入工艺。 此外，进行袋注入工艺以形成袋区域。 此后，执行第一共注入工艺以限定源极/漏极延伸区域深度分布。 然后，形成p型源极/漏极延伸区域。 之后，执行第二共注入处理以限定源极/漏极区域深度分布。 此后，进行原位掺杂外延生长工艺以形成用作p型源/漏区的掺杂半导体化合物。

公开(公告)号：US20080237734A1

公开(公告)日：2008-10-02

申请号：US11693470

申请日：2007-03-29

申请人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

发明人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor.

摘要翻译： 提供了包括基板，第一导电型MOS晶体管，第二导电型MOS晶体管，缓冲层，第一应力层和第二应力层的互补金属氧化物半导体（CMOS）晶体管。 衬底在其中具有限定第一有源区和第二有源区的器件隔离结构。 第一导电型MOS晶体管和第二导电型MOS晶体管分别设置在基板的第一有源区域和第二有源区域中。 第一导电型MOS晶体管的第一氮化物间隔物的厚度大于第二导电型MOS晶体管的第二氮化物间隔物的厚度。 缓冲层设置在第一导电型MOS晶体管上。 第一应力层设置在缓冲层上。 第二应力层设置在第二导电型MOS晶体管上。

公开(公告)号：US20080093627A1

公开(公告)日：2008-04-24

申请号：US11927642

申请日：2007-10-29

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L29/778

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 栅介质层形成在衬底的有源区上。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化物间隔物。 进行离子注入以形成源极/漏极区域。 在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。 去除氮化物间隔物。 与衬垫相邻的氮化物覆盖层被沉积。 氮化物盖层具有特定的应力状态。

公开(公告)号：US07294541B2

公开(公告)日：2007-11-13

申请号：US11163470

申请日：2005-10-20

申请人： Li-Shian Jeng ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng ,  Tzermin Shen ,  Da-Ching Cho

发明人： Li-Shian Jeng ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng ,  Tzermin Shen ,  Da-Ching Cho

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/324 ,  H01L21/28167 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating a gate dielectric layer is described. First, a well is produced in a substrate. Later, the substrate is cleaned. Then the substrate is processed by a pre-annealed process. Afterwards, a gate dielectric layer is formed on the substrate. As a result, the on-current of the semiconductor device can be increased.

摘要翻译： 描述了制造栅介质层的方法。 首先，在底物中产生孔。 之后，清洗基板。 然后通过预退火工艺处理衬底。 之后，在基板上形成栅介质层。 结果，可以提高半导体器件的导通电流。

公开(公告)号：US20070235770A1

公开(公告)日：2007-10-11

申请号：US11399827

申请日：2006-04-07

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

公开(公告)号：US09166020B2

公开(公告)日：2015-10-20

申请号：US13037383

申请日：2011-03-01

申请人： Chan-Lon Yang ,  Chi-Mao Hsu ,  Chun-Yuan Wu ,  Tzyy-Ming Cheng ,  Shih-Fang Tzou ,  Chin-Fu Lin ,  Hsin-Fu Huang ,  Min-Chuan Tsai

发明人： Chan-Lon Yang ,  Chi-Mao Hsu ,  Chun-Yuan Wu ,  Tzyy-Ming Cheng ,  Shih-Fang Tzou ,  Chin-Fu Lin ,  Hsin-Fu Huang ,  Min-Chuan Tsai

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/165

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

摘要翻译： 一种金属栅极结构的制造方法，其特征在于，具备在其上依次形成有高K栅极电介质层和底部阻挡层的基板，在基板上形成功函数金属层，对功函数金属层进行退火处理 原位。

公开(公告)号：US08765561B2

公开(公告)日：2014-07-01

申请号：US13154396

申请日：2011-06-06

申请人： Wen-Han Hung ,  Tsai-Fu Chen ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

发明人： Wen-Han Hung ,  Tsai-Fu Chen ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成虚拟栅极; 在所述伪栅极和所述衬底上形成接触蚀刻停止层; 执行平面化处理以部分地去除接触蚀刻停止层; 部分去除虚拟门; 并对接触蚀刻停止层进行热处理。