公开(公告)号：US20110063904A1

公开(公告)日：2011-03-17

申请号：US12879157

申请日：2010-09-10

Applicant: Sang-Hoan CHANG ,  Seong-Moo HEO ,  Kwang-Suk YU ,  Yeong-Taek LEE ,  Woo-Yeong CHO

Inventor： Sang-Hoan CHANG ,  Seong-Moo HEO ,  Kwang-Suk YU ,  Yeong-Taek LEE ,  Woo-Yeong CHO

IPC: G11C11/21 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0057 ,  G11C2013/0092 ,  G11C2213/56

Abstract: A method of programming a phase change memory device is disclosed. Write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells. A number of applications for the at least one verification pulse and the intervals between respective applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.

Abstract translation: 公开了一种编程相变存储器件的方法。 通过向多个相变存储单元中的每一个施加写脉冲，将写数据编程在多个相变存储单元中。 通过对每个相变存储单元施加至少一个验证脉冲来验证每个相变存储器单元是否被编程。 至少一个验证脉冲的应用程序和至少一个验证脉冲的相应应用之间的间隔的数量根据每个相变存储单元的验证结果而变化。

公开(公告)号：US07848155B2

公开(公告)日：2010-12-07

申请号：US12165861

申请日：2008-07-01

Applicant: Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

Inventor： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/3404 ,  G11C16/349 ,  G11C29/82

Abstract: Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller.

Abstract translation: 操作非易失性存储器件的方法可以补偿在块擦除操作期间由开销数据编程引起的阈值电压干扰。 这些方法包括擦除非易失性存储器单元的备用阵列和与备用阵列共享字线的非易失性存储单元的相应主阵列。 这种擦除操作之后是将更新的开销数据（例如，擦除计数）写入备用阵列中，然后执行软程序操作。 该软编程操作在主阵列的至少第一部分上执行，从而缩小主阵列的第一部分内的擦除的存储器单元的阈值电压分布。 然后，软程序操作之后是至少验证主阵列的第一部分的擦除状态的操作以及用于通知非易失性存储器单元的主阵列和备用阵列已经被适当地擦除到存储器控制器的操作。

公开(公告)号：US07692970B2

公开(公告)日：2010-04-06

申请号：US11943887

申请日：2007-11-21

Applicant: Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C11/34

CPC classification number: G11C16/344 ,  G11C16/3454

Abstract: Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

Abstract translation: 公开了一种验证闪速存储器件的编程状态的方法，其包括：响应于存储器单元的编程/擦除循环的数量确定额外的验证电压的电平; 对初始验证电压低于附加验证电压的程序存储单元执行验证操作; 以及响应于所述编程/擦除周期的数量，选择性地对所述经过程序验证的存储器单元执行附加验证电压的附加验证操作。

公开(公告)号：US07675783B2

公开(公告)日：2010-03-09

申请号：US12035732

申请日：2008-02-22

Applicant: Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C16/04

CPC classification number: G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

Abstract: Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.

Abstract translation: 提供一种非易失性存储装置及其驱动方法。 在驱动非易失性存储器件的方法中，确定要驱动的存储单元的结构形状和位置，然后使用确定结果根据存储单元的分布以优化的操作条件驱动存储单元。

公开(公告)号：US07633096B2

公开(公告)日：2009-12-15

申请号：US11461681

申请日：2006-08-01

Applicant: Ki-Whan Song ,  Yeong-Taek Lee

Inventor： Ki-Whan Song ,  Yeong-Taek Lee

IPC: H01L23/62

CPC classification number: H01L27/0262

Abstract: A Silicon-Controlled Rectifier (SCR) for Electrostatic Discharge (ESD) protection includes an isolation device. The isolation device isolates a main ground voltage line, connected to a first cathode, from a peripheral ground voltage line, connected to a second cathode. As result, even when noise occurs in the peripheral ground voltage line during the operation of an integrated circuit, the main ground voltage line maintains a stable voltage level.

Abstract translation: 用于静电放电（ESD）保护的硅控整流器（SCR）包括隔离装置。 隔离装置将连接到第一阴极的主接地电压线与连接到第二阴极的外围接地电压线隔离。 因此，即使在集成电路的动作中，外围接地电压线发生噪声时，主接地电压线保持稳定的电压电平。

公开(公告)号：US20090168534A1

公开(公告)日：2009-07-02

申请号：US12343636

申请日：2008-12-24

Applicant: Ki-Tae PARK ,  Yeong-Taek LEE

Inventor： Ki-Tae PARK ,  Yeong-Taek LEE

IPC: G11C16/06 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C16/0483 ,  G11C5/02 ,  G11C5/025 ,  G11C8/14 ,  G11C8/18 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

Abstract: Disclosed is a 3D memory device including a first plane having a first mat formed on a first layer and a third mat formed on a second layer disposed over the first layer, the first and third mats sharing a bit line, and a second plane having a second mat formed on the first layer and a fourth mat formed on the second layer. The second and fourth mats share a bit line. Each one of the first through fourth mats includes a plurality of blocks and a block associated with the first plane is simultaneously accessed with a block of the second plane.

Abstract translation: 公开了一种3D存储器件，其包括具有形成在第一层上的第一垫的第一平面和形成在第一层上的第二层上的第三垫，第一和第三垫共享位线，第二平面具有 形成在第一层上的第二垫和形成在第二层上的第四垫。 第二和第四垫共享一点。 第一至第四垫中的每一个包括多个块，并且与第一平面相关联的块与第二平面的块同时访问。

公开(公告)号：US20090168533A1

公开(公告)日：2009-07-02

申请号：US12343632

申请日：2008-12-24

Applicant: Ki-Tae PARK ,  Yeong-Taek LEE

Inventor： Ki-Tae PARK ,  Yeong-Taek LEE

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/0483 ,  G11C5/02 ,  G11C8/14 ,  G11C16/10 ,  H01L21/8221 ,  H01L27/115 ,  H01L27/11578

Abstract: A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage, and thereafter programming a selected string associated with a selected layer in the plurality of layers.

Abstract translation: 公开了一种编程方法和三维存储器件。 三维存储器件包括堆叠的多个层，每个层具有存储器阵列，并且每个存储器阵列具有一串存储器单元。 编程方法包括对于与多个层中的未选择层相关联的每个未选择的字符串，对具有关闭电压的与未选择的字符串相关联的存储器单元的通道进行充电，然后对与所选择的层相关联的所选字符串进行编程 多层。

公开(公告)号：US07551480B2

公开(公告)日：2009-06-23

申请号：US11637791

申请日：2006-12-13

Applicant: Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

Inventor： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC: G11C11/34

CPC classification number: G11C16/0408 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A flash memory device comprises a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

Abstract translation: 闪存器件包括多个存储器块。 多个存储块中选择的存储块包括2n页的数据。 所选存储块包括能够存储不同位数的不同类型的存储单元。

公开(公告)号：US20090122606A1

公开(公告)日：2009-05-14

申请号：US12348168

申请日：2009-01-02

Applicant: Dong-Hwan KIM ,  Yeong-Taek LEE

Inventor： Dong-Hwan KIM ,  Yeong-Taek LEE

IPC: G11C16/06 ,  G11C16/00

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

Abstract: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

Abstract translation: 提供了一种具有多电平单元的闪存器件及其读取和编程方法。 具有多电平单元的闪速存储器件包括存储单元阵列，用于对位线进行预充电的单元，用于向位线提供电压的位线电压供应电路，以及每个都执行与位线不同的功能的第一至第三锁存电路 彼此。 读取和编程方法由LSB和MSB读取和编程操作执行。 通过读取LSB两次并通过读取MSB一次来实现存储器件中的读取方法。 通过编程LSB一次并编程MSB一次来实现编程方法。 具有多级数据的数据可以通过两次编程操作被编程到存储器单元中。

公开(公告)号：US20090010073A1

公开(公告)日：2009-01-08

申请号：US12165861

申请日：2008-07-01

Applicant: Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

Inventor： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

IPC: G11C16/06 ,  G11C8/00

CPC classification number: G11C16/3404 ,  G11C16/349 ,  G11C29/82

Abstract: Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller.

Abstract translation: 操作非易失性存储器件的方法可以补偿在块擦除操作期间由开销数据编程引起的阈值电压干扰。 这些方法包括擦除非易失性存储器单元的备用阵列和与备用阵列共享字线的非易失性存储单元的相应主阵列。 这种擦除操作之后是将更新的开销数据（例如，擦除计数）写入备用阵列中，然后执行软程序操作。 该软编程操作在主阵列的至少第一部分上执行，从而缩小主阵列的第一部分内的擦除的存储器单元的阈值电压分布。 然后，软程序操作之后是至少验证主阵列的第一部分的擦除状态的操作以及用于通知非易失性存储器单元的主阵列和备用阵列已经被适当地擦除到存储器控制器的操作。