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公开(公告)号：US20110045651A1
公开(公告)日：2011-02-24
申请号：US12915683
申请日：2010-10-29
IPC分类号： H01L21/762
CPC分类号： H01L21/28273 , H01L21/76232 , H01L27/115 , H01L27/11521
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
摘要翻译： 一种方法包括以下步骤：将绝缘膜引入沟槽以提供沟槽隔离; 平坦化沟槽隔离以暴露钝化膜; 以及去除所述钝化膜并在第一硅层上沉积第二硅层和所述沟槽隔离; 并且在沉积第一硅层的步骤中，第一硅层是未掺杂的硅层，并且在沉积第二硅层的步骤中，第二硅层是掺杂硅层或随后具有引入杂质的未掺杂硅层，或 并且通过随后的热滞后热扩散到第一硅层中。
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公开(公告)号：US07859909B2
公开(公告)日：2010-12-28
申请号：US12546062
申请日：2009-08-24
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
摘要翻译： 对应于每个字线提供的子解码器元件由相同的导电型MOS晶体管构成。 子解码器元件布置在多个列中，使得用于形成子解码器元件的有源区域的布局在Y方向上反转并且沿着X方向被一个子解码器元件移位。 调整副解码器元件的布置，使得高电压不施加到在Y方向上相邻的两个栅电极。 用于形成子解码器元件组的阱区的阱电压被设置为电压电平，使得子解码器元件的晶体管的源极到衬底被设置为深的反向偏置状态。 在非易失性半导体存储器件中，可以抑制在供给正或负高电压的子解码器电路或字线驱动电路中的寄生MOS的泄漏。
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公开(公告)号：US07846788B2
公开(公告)日：2010-12-07
申请号：US12643646
申请日：2009-12-21
IPC分类号： H01L21/8232
CPC分类号： H01L21/28273 , H01L21/76232 , H01L27/115 , H01L27/11521
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
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公开(公告)号：US20070290271A1
公开(公告)日：2007-12-20
申请号：US11808959
申请日：2007-06-14
申请人： Yoshihiko Kusakabe
发明人： Yoshihiko Kusakabe
IPC分类号： H01L29/76
CPC分类号： H01L27/105 , H01L21/823462 , H01L21/823481 , H01L27/11526 , H01L27/11534
摘要： The semiconductor device whose yield and reliability improved, and its manufacturing method are offered.A resist layer is formed so that the silicon nitride film and filling insulating film in region A may be covered. Then, in order to adjust the height position of the upper surface of a filling insulating film, a plasma etch back or fluoric acid is performed. Thereby, the filling insulating film on the silicon nitride film in region B is removed. Therefore, the problem that the residue of a filling insulating film remains on the silicon nitride film in region B is solved.
摘要翻译： 提高了产量和可靠性的半导体器件及其制造方法。 形成抗蚀剂层，从而可以覆盖区域A中的氮化硅膜和填充绝缘膜。 然后，为了调整填充绝缘膜的上表面的高度位置，进行等离子体回蚀或氟酸。 由此，去除区域B中的氮化硅膜上的填充绝缘膜。 因此，解决了填充绝缘膜残留在区域B中的氮化硅膜上的问题。
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公开(公告)号：US20120080757A1
公开(公告)日：2012-04-05
申请号：US13376081
申请日：2009-06-05
申请人： Hisayuki Kato , Yoshihiko Kusakabe
发明人： Hisayuki Kato , Yoshihiko Kusakabe
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823814 , H01L21/823864 , H01L22/26 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： First protective films are formed to cover side surfaces of gate electrode portions. In an nMOS region, an extention implantation region is formed by causing a portion of the first protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as a mask, and then, cleaning is done. Since silicon nitride films are formed on surfaces of the first protective films, the resistance to chemical solutions is improved. Furthermore, second protective films are formed on the first protective films, respectively. In a pMOS region, an extention implantation region is formed by causing a portion of the first protective film and a portion of the second protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as the mask, and then, cleaning is done.
摘要翻译： 形成第一保护膜以覆盖栅电极部分的侧表面。 在nMOS区域中，通过使位于栅极电极部分的侧表面上的第一保护膜的一部分用作偏移间隔物并使用偏移间隔物作为掩模来形成延伸注入区域，然后清洁 完成了 由于在第一保护膜的表面上形成氮化硅膜，因此提高了对化学溶液的耐性。 此外，在第一保护膜上分别形成第二保护膜。 在pMOS区域中，通过使第一保护膜的一部分和位于栅极电极部分的侧表面上的第二保护膜的一部分用作偏移间隔物并使用偏移间隔物形成延伸注入区 面具，然后进行清洁。
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公开(公告)号：US07411834B2
公开(公告)日：2008-08-12
申请号：US11701404
申请日：2007-02-02
摘要： A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
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公开(公告)号：US09449883B2
公开(公告)日：2016-09-20
申请号：US13376081
申请日：2009-06-05
申请人： Hisayuki Kato , Yoshihiko Kusakabe
发明人： Hisayuki Kato , Yoshihiko Kusakabe
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238 , H01L21/66 , H01L29/51 , H01L29/66
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823814 , H01L21/823864 , H01L22/26 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： First protective films are formed to cover side surfaces of gate electrode portions. In an nMOS region, an extention implantation region is formed by causing a portion of the first protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as a mask, and then, cleaning is done. Since silicon nitride films are formed on surfaces of the first protective films, the resistance to chemical solutions is improved. Furthermore, second protective films are formed on the first protective films, respectively. In a pMOS region, an extention implantation region is formed by causing a portion of the first protective film and a portion of the second protective film located on the side surface of the gate electrode portion to function as an offset spacer and using the offset spacer as the mask, and then, cleaning is done.
摘要翻译： 形成第一保护膜以覆盖栅电极部分的侧表面。 在nMOS区域中，通过使位于栅极电极部分的侧表面上的第一保护膜的一部分用作偏移间隔物并使用偏移间隔物作为掩模来形成延伸注入区域，然后清洁 完成了 由于在第一保护膜的表面上形成氮化硅膜，因此提高了对化学溶液的耐性。 此外，在第一保护膜上分别形成第二保护膜。 在pMOS区域中，通过使第一保护膜的一部分和位于栅极电极部分的侧表面上的第二保护膜的一部分用作偏移间隔物并使用偏移间隔物形成延伸注入区 面具，然后进行清洁。
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公开(公告)号：US08614469B2
公开(公告)日：2013-12-24
申请号：US13605995
申请日：2012-09-06
IPC分类号： H01L29/76
CPC分类号： H01L21/823412 , H01L21/28052 , H01L21/823468 , H01L21/823807 , H01L27/088 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate.
摘要翻译： 提供了能够提高驱动能力的半导体装置及其制造方法。 在半导体器件中，通过连续堆叠栅极氧化膜和硅层形成的栅极结构布置在半导体衬底上。 在栅极结构的侧面设置氧化膜的长度较长，另一方的氧化膜沿着氧化膜的侧面和基板的上表面配置。 在包含这些氧化物膜的侧壁氧化物膜中，沿着栅极结构的横向侧的第一层的厚度的最小值小于沿着衬底的上表面的第二层的厚度。
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公开(公告)号：US20050287777A1
公开(公告)日：2005-12-29
申请号：US11159389
申请日：2005-06-23
IPC分类号： H01L21/00 , H01L21/04 , H01L21/28 , H01L21/762 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/76232 , H01L27/115 , H01L29/40114
摘要： A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
摘要翻译： 一种方法包括以下步骤：将绝缘膜引入沟槽以提供沟槽隔离; 平坦化沟槽隔离以暴露钝化膜; 以及去除所述钝化膜并在第一硅层上沉积第二硅层和所述沟槽隔离; 并且在沉积第一硅层的步骤中，第一硅层是未掺杂的硅层，并且在沉积第二硅层的步骤中，第二硅层是掺杂硅层或随后具有引入杂质的未掺杂硅层，或 并且通过随后的热滞后热扩散到第一硅层中。
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公开(公告)号：US06472324B2
公开(公告)日：2002-10-29
申请号：US09809184
申请日：2001-03-16
申请人： Yoshihiko Kusakabe , Yasuki Morino
发明人： Yoshihiko Kusakabe , Yasuki Morino
IPC分类号： H01L21302
CPC分类号： H01L21/76224 , H01L21/31053 , H01L21/31612 , H01L21/31662
摘要： The present invention is directed to a method of manufacturing a trench type semiconductor element isolation structure including the steps of: (i) forming a silicon oxide film on a silicon substrate and forming a silicon nitride film on the silicon oxide film; (ii) forming a groove penetrating the silicon nitride film and the silicon oxide film, said groove reaching an interior of the silicon substrate; (iii) forming a thermal oxide film on an inner wall of said groove; (iv) depositing an oxide in said groove; (v) subjecting said oxide to a polishing treatment with the silicon nitride film used as a stopper layer, so that a part of the insulator is removed; (vi) etching the oxide by a predetermined amount of said oxide after completing the step (v); (vii) etching the silicon nitride film after completing the step (vi); and (viii) etching the silicon oxide film after completing the step (vii).
摘要翻译： 本发明涉及一种制造沟槽型半导体元件隔离结构的方法，包括以下步骤：（i）在硅衬底上形成氧化硅膜并在氧化硅膜上形成氮化硅膜; （ii）形成贯穿所述氮化硅膜和所述氧化硅膜的槽，所述槽到达所述硅衬底的内部; （iii）在所述槽的内壁上形成热氧化膜; （iv）在所述槽中沉积氧化物; （v）对所述氧化物进行抛光处理，所述氮化硅膜用作阻挡层，从而去除绝缘体的一部分; （vi）在完成步骤（v）之后，用预定量的氧化物蚀刻氧化物; （vii）在完成步骤（vi）之后蚀刻氮化硅膜; 和（viii）在完成步骤（vii）之后蚀刻氧化硅膜。
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