公开(公告)号：US12231120B1

公开(公告)日：2025-02-18

申请号：US17855562

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadeesh Anathahalli Singrigowda ,  Girish A S ,  Aniket Bharat Waghide ,  Prasant Kumar Vallur

IPC: H03K19/00 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3234 ,  G06F1/3296 ,  G06K15/00 ,  H03K3/037 ,  H03K19/17736

Abstract: A disclosed method for improving latency or power consumption may include (i) receiving, at a power-state processing circuit, a power-state signal indicating whether a processing unit is entering a low-power-state, (ii) transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit, and (iii) storing, by the latching circuit and in response to the control signal, a state of an input/output pad that is coupled to the processing unit. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US12088296B2

公开(公告)日：2024-09-10

申请号：US17554722

申请日：2021-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ramon A. Mangaser ,  Srikanth Reddy Gruddanti ,  Prasant Kumar Vallur ,  Krishna Reddy Mudimela Venkata ,  Oikwan Tsang

IPC: H03K19/20 ,  G06F1/06 ,  H03K3/037

CPC classification number: H03K19/20 ,  G06F1/06 ,  H03K3/037

Abstract: A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.

公开(公告)号：US11569819B1

公开(公告)日：2023-01-31

申请号：US17486466

申请日：2021-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Dhruvin Devangbhai Shah ,  Jagadeesh Anathahalli Singrigowda ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K19/00 ,  H03K19/0185 ,  H03K3/356 ,  H03K19/003 ,  H03K3/012

Abstract: A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

公开(公告)号：US11418189B2

公开(公告)日：2022-08-16

申请号：US17081540

申请日：2020-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadeesh Anathahalli Singrigowda ,  Ashish Sahu ,  Rajesh Mangalore Anand ,  Aniket Bharat Waghide ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K19/0948 ,  H03K17/687 ,  H03K19/0185 ,  G05F3/20 ,  H03K19/003 ,  H03K17/0812 ,  G01R19/165

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.