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    PARALLEL SCHEDULING OF WRITE COMMANDS TO MULTIPLE MEMORY DEVICES
    11.
    发明申请
    PARALLEL SCHEDULING OF WRITE COMMANDS TO MULTIPLE MEMORY DEVICES 有权

    公开(公告)号：US20170255396A1

    公开(公告)日：2017-09-07

    申请号：US15057145

    申请日：2016-03-01

    Applicant: Apple Inc.

    Inventor： Yoni Labenski ,  Roman Gindin ,  Etai Zaltsman ,  Moti Altahan ,  Yoram Harel ,  Barak Baum

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0688

    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.

    NOTIFICATION OF STORAGE DEVICE PERFORMANCE TO HOST
    12.
    发明申请
    NOTIFICATION OF STORAGE DEVICE PERFORMANCE TO HOST 审中-公开
    存储设备对主机性能的通知

    公开(公告)号：US20140359198A1

    公开(公告)日：2014-12-04

    申请号：US13903298

    申请日：2013-05-28

    Applicant: Apple Inc.

    Inventor： Etai Zaltsman ,  Ori Moshe Stern ,  Sasha Paley

    IPC: G06F12/02

    CPC classification number: G06F3/0688 ,  G06F3/0605 ,  G06F3/064 ,  G06F3/0653

    Abstract: A method includes, in a storage device that stores data for a host in a memory, estimating an impact of an amount of free memory space in the memory on a storage performance of the storage device. The storage device sends to the host a notification that is indicative of the estimated impact.

    Abstract translation: 一种方法包括在将主机的数据存储在存储器中的存储设备中，估计存储器中的可用存储器空间量对存储设备的存储性能的影响。 存储设备向主机发送指示估计影响的通知。

    Accelerator circuit for mathematical operations with immediate values table
    13.
    发明授权
    Accelerator circuit for mathematical operations with immediate values table 有权

    公开(公告)号：US11614937B1

    公开(公告)日：2023-03-28

    申请号：US17566193

    申请日：2021-12-30

    Applicant: Apple Inc.

    Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan ,  Etai Zaltsman

    IPC: G06F9/30

    Abstract: Embodiments of the present disclosure relate to an accelerator circuit with a dynamic immediate values table (IVT). The accelerator circuit includes an instruction memory, a data memory, and a vector circuit with the IVT storing multiple immediate values at multiple entries. The vector circuit reads a subset of instructions from the instruction memory, each instruction including at least one corresponding pointer to at least one corresponding entry in the IVT. The vector circuit further receives a subset of input data from the data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction from the subset of instructions using a corresponding data vector of the received subset of input data identified in each instruction and at least one corresponding immediate value from the IVT pointed by the at least one corresponding pointer to generate corresponding output data.

    MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION
    16.
    发明申请
    MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION 审中-公开
    在长期静态和擦除状态下，减轻模拟记忆细胞的可靠性降低

    公开(公告)号：US20160093386A1

    公开(公告)日：2016-03-31

    申请号：US14962333

    申请日：2015-12-08

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Moshe Neerman ,  Naftali Sommer ,  Avraham Poza Meir ,  Etai Zaltsman ,  Eyal Gurgi ,  Meir Dalal

    IPC: G11C16/14

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

    Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

    Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元被设置为与擦除的电平不同的保持编程电平。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。

    PROTECTION AND RECOVERY FROM SUDDEN POWER FAILURE IN NON-VOLATILE MEMORY DEVICES
    17.
    发明申请
    PROTECTION AND RECOVERY FROM SUDDEN POWER FAILURE IN NON-VOLATILE MEMORY DEVICES 有权
    非易失性存储器件中的电源故障的保护和恢复

    公开(公告)号：US20160011806A1

    公开(公告)日：2016-01-14

    申请号：US14523979

    申请日：2014-10-27

    Applicant: Apple Inc.

    Inventor： Etai Zaltsman ,  Avraham Poza Meir

    IPC: G06F3/06 ,  G06F11/14 ,  G11C11/56

    CPC classification number: G06F3/0619 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1441 ,  G11C11/5628 ,  G11C16/22 ,  G11C16/225 ,  G11C27/005 ,  G11C2211/5641

    Abstract: A method for data storage includes, for a memory including groups of memory cells, defining a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell. Data is initially stored in the memory using the normal mode. In response to an event, the protected mode is reverted to for at least one of the groups of the memory cells.

    Abstract translation: 一种用于数据存储的方法包括：定义正常模式和保护模式的包括存储器单元组的存储器，其中在保护模式中，每个存储单元的相应模拟值始终保持明确地指示存储的相应数据值 在那个记忆体中。 数据最初使用普通模式存储在存储器中。 响应于事件，保护模式被恢复为存储器单元的组中的至少一个。

    EFFICIENT ENFORCEMENT OF COMMAND EXECUTION ORDER IN SOLID STATE DRIVES
    18.
    发明申请
    EFFICIENT ENFORCEMENT OF COMMAND EXECUTION ORDER IN SOLID STATE DRIVES 审中-公开
    有效执行固态执法机构的命令执行令

    公开(公告)号：US20150331638A1

    公开(公告)日：2015-11-19

    申请号：US14813436

    申请日：2015-07-30

    Applicant: Apple Inc.

    Inventor： Etai Zaltsman ,  Oren Golov ,  Ori Moshe Stern ,  Shai Ojalvo

    IPC: G06F3/06 ,  G06F13/28

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0623 ,  G06F3/0679 ,  G06F13/28

    Abstract: A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.

    Abstract translation: 存储装置中的方法包括从主机存储命令以在存储装置的非易失性存储器中执行。 存储命令的至少一个子集将根据接收到的子集中的存储命令的到达顺序被执行。 接收到的存储命令根据存储设备的内部调度标准在非易失性存储器中执行，这允许偏离到达顺序，但是使得子集中的存储命令的执行反映了 适合主机。

    Parallel scheduling of write commands to multiple memory devices
    19.
    发明授权
    Parallel scheduling of write commands to multiple memory devices 有权

    公开(公告)号：US09952779B2

    公开(公告)日：2018-04-24

    申请号：US15057145

    申请日：2016-03-01

    Applicant: Apple Inc.

    Inventor： Yoni Labenski ,  Roman Gindin ,  Etai Zaltsman ,  Moti Altahan ,  Yoram Harel ,  Barak Baum

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0688

    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.

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