公开(公告)号：US10388394B2

公开(公告)日：2019-08-20

申请号：US15658430

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Yonathan Tate ,  Tomer Ish-Shalom

IPC: G11C29/00 ,  G11C29/42 ,  G06F11/10 ,  G11C29/44

Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to read from a group of the memory cells a code word encoded using an Error Correction Code (ECC), by sensing the memory cells using at least first and second read thresholds for producing respective first and second readouts, to calculate, based on at least one of the first and second readouts, (i) a syndrome weight that is indicative of an actual number of errors contained in the code word, and (ii) a mid-zone count of the memory cells for which the first readout differs from the second readout, and, to evaluate a performance measure for the memory cells, based on the calculated syndrome weight and mid-zone count.

公开(公告)号：US09971646B2

公开(公告)日：2018-05-15

申请号：US15169825

申请日：2016-06-01

Applicant: Apple Inc.

Inventor： Moti Teitel ,  Tomer Ish-Shalom

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/11 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1148

Abstract: A storage device includes a memory that includes storage circuitry and a memory including multiple memory cells. The storage circuitry is configured to store in a group of the memory cells data that was encoded using an error correcting code (ECC) consisting of multiple component codes, to define multiple threshold settings, each specifying positions of one or more reading-thresholds, to read the data from the memory cells in the group using the threshold settings and decode the read data using the component codes, to calculate for the component codes respective component-code scores that are indicative of levels of confidence in the decoded data of the component-codes, to select, based on the component-code scores, a threshold setting that is expected to result in a best readout performance among the multiple threshold settings, and to read data from the memory using the selected threshold setting.

公开(公告)号：US09236890B1

公开(公告)日：2016-01-12

申请号：US14569716

申请日：2014-12-14

Applicant: APPLE INC.

Inventor： Micha Anholt ,  Moti Teitel ,  Tomer Ish-Shalom

IPC: H03M13/00 ,  H03M13/47 ,  H03M13/29 ,  H04L1/00

CPC classification number: H03M13/2906 ,  H03M13/00 ,  H03M13/152 ,  H03M13/153 ,  H03M13/2927 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/45 ,  H03M13/453 ,  H04L1/0057

Abstract: A method for decoding includes receiving channel inputs for respective bits of a super code word that includes at least first and second component code words having a shared group of bits. At least the first and second component code words are iteratively decoded, and, in response to recognizing that the first and second component code words contain errors only within the shared group of bits, the first and second component code words are jointly decoded.

Abstract translation: 一种解码方法包括接收包含至少具有共享比特组的第一和第二分量码字的超级码字的各个比特的信道输入。 至少第一和第二分量代码字被迭代地解码，并且响应于识别出第一和第二分量代码字仅在共享的位组内包含错误，第一和第二分量代码字被联合解码。

公开(公告)号：US20150180511A1

公开(公告)日：2015-06-25

申请号：US14138809

申请日：2013-12-23

Applicant: Apple Inc.

Inventor： Tomer Ish-Shalom ,  Ronen Dar ,  Micha Anholt

IPC: H03M13/37

CPC classification number: H03M13/1111 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/3715

Abstract: A method includes decoding a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations, such that each iteration involves processing of multiple variable nodes. For one or more selected variable nodes, a count of the check equations that are defined over one or more variables held respectively by the one or more selected variable nodes is evaluated, and, when the count meets a predefined skipping criterion, the one or more selected variable nodes are omitted from a given iteration in the sequence.

Abstract translation: 一种方法包括通过执行一系列迭代来解码纠错码（ECC）的代码字，其可由一组检验方程表示，使得每次迭代涉及多个可变节点的处理。 对于一个或多个选定的变量节点，评估在一个或多个所选变量节点分别保存的一个或多个变量上定义的检验方程的计数，并且当该计数满足预定的跳过标准时，该一个或多个 在序列中给定的迭代中省略了选定的变量节点。

公开(公告)号：US20140331106A1

公开(公告)日：2014-11-06

申请号：US13874995

申请日：2013-05-01

Applicant: APPLE INC.

Inventor： Barak Baum ,  Tomer Ish-Shalom ,  Micha Anholt ,  Eyal Gurgi ,  Yoav Kasorla

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1076 ,  G11C7/14 ,  G11C11/5621 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42

Abstract: A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a first part of the code word is stored in a first memory unit and a second part of the code word is stored in a second memory unit. A subset of the check equations, which operate only on code word bits belonging to the first part stored in the first memory unit, is identified. The first part of the code word is retrieved from the first memory unit, and a count of the check equations in the identified subset that are not satisfied by the retrieved first part of the code word is evaluated. One or more readout parameters, for readout from the first memory unit, are set depending on the evaluated count.

Abstract translation: 一种方法包括在包括两个或多个存储器单元的存储器中，存储可由多个检验方程表示的纠错码（ECC）的代码字，使得代码字的第一部分被存储在 第一存储单元和码字的第二部分被存储在第二存储单元中。 识别仅对属于存储在第一存储器单元中的第一部分的代码字位操作的检验方程的子集。 从第一存储器单元检索代码字的第一部分，并且对所检索的代码字的第一部分不满足的所识别的子集中的检验方程的计数进行评估。 根据评估计数来设定用于从第一存储器单元读出的一个或多个读出参数。

公开(公告)号：US20140089754A1

公开(公告)日：2014-03-27

申请号：US13628321

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Tomer Ish-Shalom ,  Micha Anholt

IPC: H03M13/00

CPC classification number: H03M13/1111 ,  H03M13/1117 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1154

Abstract: A method includes, in a decoder of an Error Correction Code (ECC), maintaining only aggregated information regarding a set of messages, a function of which is to be reported from a first node to a second node of the decoder. The function of the set is determined and reported using the aggregated information. After reporting the function, one of the messages in the set is replaced with a new message. The aggregated information is updated to reflect the set having the new message, and the function of the set having the new message is determined and reported using the updated aggregated information.

Abstract translation: 一种方法包括在纠错码（ECC）的解码器中维护关于一组消息的聚合信息，其功能将从解码器的第一节点报告给第二节点。 使用聚合信息确定并报告集合的功能。 报告功能后，集合中的消息之一将被替换为新消息。 聚合信息被更新以反映具有新消息的集合，并且使用更新的聚合信息确定并报告具有新消息的集合的功能。

公开(公告)号：US10193574B1

公开(公告)日：2019-01-29

申请号：US15158620

申请日：2016-05-19

Applicant: APPLE INC.

Inventor： Moti Teitel ,  Asaf Landau ,  Tomer Ish-Shalom

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/11 ,  H04L1/00 ,  H03M13/29 ,  G11B20/18 ,  G06F11/10

Abstract: An apparatus includes an interface, main and secondary processing modules, and circuitry. The interface is configured to receive input data to be processed in accordance with a GLDPC code defined by a parity-check-matrix including multiple sub-matrices, each sub-matrix including a main diagonal and one or more secondary diagonals, and each of the main and secondary diagonals includes N respective block matrices. The main processing module is configured to calculate N first partial syndromes based on the input data and on the block matrices of the main diagonals. The secondary processing module is configured to calculate N second partial syndromes based on the input data and on the block matrices of the secondary diagonals. The circuitry is configured to produce N syndromes by respectively combining the N first partial syndromes with the N second partial syndromes, and to encode or decode the input data, based on the N syndromes.

公开(公告)号：US09553611B2

公开(公告)日：2017-01-24

申请号：US14555608

申请日：2014-11-27

Applicant: APPLE INC.

Inventor： Moti Teitel ,  Tomer Ish-Shalom

IPC: H03M13/29 ,  H03M13/00 ,  H03M13/11 ,  G06F11/10

CPC classification number: H03M13/2918 ,  G06F11/1048 ,  G06F11/1076 ,  H03M13/1148 ,  H03M13/2963 ,  H03M13/616

Abstract: A method for Error Correction Code (ECC) encoding includes receiving data to be encoded. The data is encoded to produce a composite code word that includes multiple component code words. Each component code word in at least a subset of the component code words is encoded in accordance with a respective component code and has at least one respective bit in common with each of the other component code words.

Abstract translation: 用于纠错码（ECC）编码的方法包括接收要编码的数据。 数据被编码以产生包括多个分量码字的复合码字。 在分量码字的至少一个子集中的每个分量码字根据相应的分量码进行编码，并且具有至少一个与每个其它分量码字相同的相应位。

公开(公告)号：US20160094245A1

公开(公告)日：2016-03-31

申请号：US14499284

申请日：2014-09-29

Applicant: APPLE INC.

Inventor： Asaf Landau ,  Tomer Ish-Shalom ,  Yonathan Tate

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/116 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/15 ,  H03M13/271 ,  H03M13/616 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0057

Abstract: A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.

Abstract translation: 解码器包括可变节点电路，校验节点电路和消息传递（MP）模块，消息传递（MP）模块包括多个可配置的部分循环移位器，每个移位器仅支持移位值0的全范围内的移位值的部分子集。 。 。 L-1。 可变节点电路和校验节点电路被配置为根据表示相应的准循环（QC） - 低密度奇偶校验（LDPC）纠错码（ECC）的奇偶校验矩阵和彼此之间的交换消息 其包括L乘L子矩阵，并处理所交换的消息以解码使用QC-LDPC ECC编码的给定码字。 MP模块被配置为根据相应的子矩阵来调度互连的可变节点电路和校验节点电路，以通过分配给定的部分循环移位器来周期性地移动L个消息来同时交换L个消息 这取决于相应子矩阵的结构。

公开(公告)号：US09250814B2

公开(公告)日：2016-02-02

申请号：US13763928

申请日：2013-02-11

Applicant: Apple Inc.

Inventor： Eyal Gurgi ,  Tomer Ish-Shalom

IPC: G06F13/00 ,  G06F3/06 ,  G06F13/16 ,  G11C16/06

CPC classification number: G06F3/0611 ,  G06F13/1626 ,  G11C16/06

Abstract: An apparatus includes a memory and storage circuitry. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance.

Abstract translation: 一种装置包括存储器和存储电路。 存储电路被配置为接收至少一个请求，从而在存储器中执行一系列存储器命令，以便识别尽管在第二存储器命令之前的序列中出现第一存储器命令，但是第二存储器命令的执行将 提高执行第一存储器命令的性能，并且执行第二存储器命令，然后执行具有改进的执行性能的第一存储器命令。