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    Handling malfunction in a memory system comprising a nonvolatile memory by monitoring bad-block patterns
    11.
    发明授权
    Handling malfunction in a memory system comprising a nonvolatile memory by monitoring bad-block patterns 有权

    公开(公告)号：US10936456B1

    公开(公告)日：2021-03-02

    申请号：US16280090

    申请日：2019-02-20

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Assaf Shappir ,  Stas Mouler ,  Yoav Kasorla

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/14

    Abstract: A controller includes an interface and storage circuitry. The interface communicates with one or more memory devices, each of the memory devices includes multiple memory cells organized in memory blocks. The storage circuitry is configured to perform multiple storage operations to the memory cells in the one or more memory devices, and mark memory blocks in which one or more storage operations have failed as bad blocks. The controller is further configured to identify a pattern of multiple bad blocks occurring over a sequence of multiple consecutive storage operations, the pattern is indicative of a system-level malfunction in a memory system including the controller, and in response to identifying the pattern, to perform a corrective action to the memory system.

    Data storage in a memory block following WL-WL short
    15.
    发明授权
    Data storage in a memory block following WL-WL short 有权
    数据存储在WL-WL之后的存储器块中

    公开(公告)号：US09390809B1

    公开(公告)日：2016-07-12

    申请号：US14617961

    申请日：2015-02-10

    Applicant: APPLE INC.

    Inventor： Yael Shur ,  Avraham Poza Meir ,  Barak Baum ,  Eyal Gurgi

    IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C29/00

    CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/70 ,  G11C2029/1202

    Abstract: A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage configuration, different from the normal voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block. If no WL-WL short-circuit is found in the memory block, a data storage operation is performed in the memory block by applying the normal voltage configuration. If a WL-WL short-circuit is found in the memory block, the data storage operation is performed in the memory block by applying the abnormal voltage configuration.

    Abstract translation: 一种方法包括定义用于应用于存储块的字线（WL）和位线（BL）的正常电压配置以及不同于正常电压配置的异常电压配置，以应用于WL和BL 当在存储器块中的至少两个WL之间找到字线到字线（WL-WL）短路时，存储块。 如果在存储块中没有发现WL-WL短路，则通过施加正常电压配置在存储块中执行数据存储操作。 如果在存储器块中发现WL-WL短路，则通过应用异常电压配置在存储块中执行数据存储操作。

    MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION
    16.
    发明申请
    MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION 审中-公开
    在长期静态和擦除状态下，减轻模拟记忆细胞的可靠性降低

    公开(公告)号：US20160093386A1

    公开(公告)日：2016-03-31

    申请号：US14962333

    申请日：2015-12-08

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Moshe Neerman ,  Naftali Sommer ,  Avraham Poza Meir ,  Etai Zaltsman ,  Eyal Gurgi ,  Meir Dalal

    IPC: G11C16/14

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

    Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

    Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元被设置为与擦除的电平不同的保持编程电平。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。

    ESTIMATING FLASH QUALITY USING SELECTIVE ERROR EMPHASIS
    17.
    发明申请
    ESTIMATING FLASH QUALITY USING SELECTIVE ERROR EMPHASIS 有权
    使用选择性错误来评估闪光质量

    公开(公告)号：US20160092284A1

    公开(公告)日：2016-03-31

    申请号：US14501081

    申请日：2014-09-30

    Applicant: APPLE INC.

    Inventor： Yael Shur ,  Eyal Gurgi ,  Moshe Neerman ,  Naftali Sommer

    IPC: G06F11/07

    CPC classification number: G06F11/076 ,  G06F11/073 ,  G06F11/1012 ,  G06F11/1072 ,  G11C11/5642 ,  G11C11/5692 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42

    Abstract: A method for data storage includes reading from a memory device data that is stored in a group of memory cells as respective analog values, and classifying readout errors in the read data into at least first and second different types, depending on zones in which the analog values fall. A memory quality that emphasizes the readout errors of the second type is assigned to the group of the memory cells, based on evaluated numbers of the readout errors of the first and second types.

    Abstract translation: 一种用于数据存储的方法包括：从存储器件读取作为相应模拟值存储在一组存储器单元中的数据，并将读出的数据中的读出错误分类为至少第一和第二不同类型，这取决于模拟 价值下降。 基于第一和第二类型的读出错误的评估数，将强调第二类型的读出错误的存储器质量分配给存储器单元组。

    Applications for inter-word-line programming
    18.
    发明授权
    Applications for inter-word-line programming 有权
    字间编程应用

    公开(公告)号：US08837214B2

    公开(公告)日：2014-09-16

    申请号：US13709303

    申请日：2012-12-10

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

    IPC: G11C16/04 ,  G11C7/00

    CPC classification number: G11C27/00 ,  G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

    Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.

    Abstract translation: 一种方法包括在与各个字线相关联的行中排列的模拟存储器单元的阵列中，读取选定字线中的第一组存储器单元，包括存储至少一个状态的一个或多个存储器单元 数组中除字线以外的所选字线。 响应于读取状态设置第二组存储器单元的读出配置。 使用读出配置读取第二组存储单元。

    Fast analog memory cell readout using modified bit-line charging configurations
    19.
    发明授权
    Fast analog memory cell readout using modified bit-line charging configurations 有权
    使用修改的位线充电配置快速模拟存储单元读数

    公开(公告)号：US08787057B2

    公开(公告)日：2014-07-22

    申请号：US13709656

    申请日：2012-12-10

    Applicant: Apple Inc.

    Inventor： Eyal Gurgi ,  Yael Shur ,  Yoav Kasorla

    IPC: G11C27/00

    CPC classification number: G06F12/00 ,  G06F12/02

    Abstract: A method for data storage includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.

    Abstract translation: 一种用于数据存储的方法包括提供至少第一和第二读出方案，用于从连接到各个位线的一组模拟存储器单元读取存储值。 第一读出方案使用具有第一感测时间的第一位线充电配置读取存储值，并且第二读出方案使用比第一感测时间短的具有第二感测时间的第二位线充电配置来读取存储值。 针对要在一组存储器单元上执行的读取操作来评估条件。 响应于评估条件选择第一和第二读出方案中的一个。 使用所选择的读出方案从存储器单元的组中读取存储值。

    Memory block usage based on block location relative to array edge
    20.
    发明授权
    Memory block usage based on block location relative to array edge 有权

    公开(公告)号：US10332608B2

    公开(公告)日：2019-06-25

    申请号：US15992229

    申请日：2018-05-30

    Applicant: Apple Inc.

    Inventor： Yael Shur ,  Assaf Shappir ,  Barak Baum ,  Roman Guy ,  Michael Tsohar

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08

    Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.

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