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    WORDLINE 3D FLASH MEMORY AIR GAP
    13.
    发明申请
    WORDLINE 3D FLASH MEMORY AIR GAP 审中-公开

    公开(公告)号：US20160043099A1

    公开(公告)日：2016-02-11

    申请号：US14452378

    申请日：2014-08-05

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Shankar Venkataraman ,  Nitin K. Ingle

    IPC: H01L27/115 ,  H01L21/3213 ,  H01L21/311

    CPC classification number: H01L27/11582 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67103 ,  H01L21/6719 ,  H01L21/764

    Abstract: Methods of forming air gaps in a 3-d flash memory cell using only gas-phase etching techniques are described. The methods include selectively gas-phase etching tungsten deposited into the stack structure to separate the tungsten levels. Other metals than tungsten may be used. The methods also include selectively etching silicon oxide from between the tungsten levels to make room for vertically spaced air gaps. A nonconformal silicon oxide layer is then deposited to trap the air gaps. Both tungsten removal and silicon oxide removal use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The nonconformal silicon oxide may be deposited inside or outside the mainframe.

    Abstract translation: 描述了仅使用气相蚀刻技术在3-d闪存单元中形成气隙的方法。 这些方法包括选择性地将钨沉积到堆叠结构中的钨相蚀刻钨以分离钨含量。 可以使用除钨以外的其他金属。 所述方法还包括从钨水平之间选择性地蚀刻氧化硅以为垂直间隔的气隙腾出空间。 然后沉积非共形氧化硅层以捕获气隙。 除钨和氧化硅除去都使用连接在同一主机上的远程激发的含氟装置，以便于在没有中间大气暴露的情况下进行这两种操作。 非共形氧化硅可以沉积在主机内部或外部。

    3D flash memory cells which discourage cross-cell electrical tunneling
    14.
    发明授权
    3D flash memory cells which discourage cross-cell electrical tunneling 有权

    公开(公告)号：US10541246B2

    公开(公告)日：2020-01-21

    申请号：US15966989

    申请日：2018-04-30

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath

    IPC: H01L27/11556 ,  H01L29/49

    Abstract: 3-d flash memory cells and methods of manufacture are described. The devices and methods recess a compound floating gate in between the silicon oxide slabs which reduces the quantum probability of electron tunneling between vertically adjacent storage cells. The devices and methods further include a high work function nanocrystalline metal in the compound floating gate. A polysilicon buffer layer forms a portion of the compound floating gate. The polysilicon buffer layer allows the high work function nanocrystalline metal to be selectively deposited. The polysilicon buffer layer further protects the high work function nanocrystalline metal from oxidation with the gate oxide subsequently formed on the other side.

    ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES
    15.
    发明申请
    ACCOMMODATING IMPERFECTLY ALIGNED MEMORY HOLES 审中-公开

    公开(公告)号：US20190296045A1

    公开(公告)日：2019-09-26

    申请号：US16435887

    申请日：2019-06-10

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath

    IPC: H01L27/11582 ,  H01L21/308 ,  H01L21/311 ,  H01L21/67 ,  H01L21/28 ,  H01L29/10 ,  H01L21/3065

    Abstract: Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.

    3D FLASH MEMORY CELLS WHICH DISCOURAGE CROSS-CELL ELECTRICAL TUNNELING
    16.
    发明申请
    3D FLASH MEMORY CELLS WHICH DISCOURAGE CROSS-CELL ELECTRICAL TUNNELING 审中-公开

    公开(公告)号：US20180374863A1

    公开(公告)日：2018-12-27

    申请号：US15966989

    申请日：2018-04-30

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath

    IPC: H01L27/11556 ,  H01L29/49

    Abstract: 3-d flash memory cells and methods of manufacture are described. The devices and methods recess a compound floating gate in between the silicon oxide slabs which reduces the quantum probability of electron tunneling between vertically adjacent storage cells. The devices and methods further include a high work function nanocrystalline metal in the compound floating gate. A polysilicon buffer layer forms a portion of the compound floating gate. The polysilicon buffer layer allows the high work function nanocrystalline metal to be selectively deposited. The polysilicon buffer layer further protects the high work function nanocrystalline metal from oxidation with the gate oxide subsequently formed on the other side.

    Integrated oxide recess and floating gate fin trimming
    17.
    发明授权
    Integrated oxide recess and floating gate fin trimming 有权
    集成氧化物凹槽和浮栅鳍片修整

    公开(公告)号：US09378978B2

    公开(公告)日：2016-06-28

    申请号：US14448901

    申请日：2014-07-31

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Shankar Venkataraman ,  Nitin K. Ingle

    IPC: H01L21/3213 ,  H01L21/28 ,  H01L29/40 ,  H01L29/423 ,  H01L21/677

    CPC classification number: H01L21/32137 ,  H01J37/32357 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/67739 ,  H01L21/76224 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/66825

    Abstract: Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.

    Abstract translation: 描述了在不破坏真空的情况下回蚀浅沟槽隔离（STI）电介质和修整暴露的浮动栅极的方法。 这些方法包括凹陷氧化硅电介质间隙填充以暴露多晶硅浮动栅极的垂直侧壁。 然后对暴露的垂直侧壁进行各向同性蚀刻，以在相同的基板处理主机上均匀地稀薄多晶硅浮动栅极。 凹陷氧化硅和各向同性蚀刻多晶硅都使用连接在同一主机上的远程激发的含氟设备，以便于在没有中间大气暴露的情况下进行两种操作。 然后可将多晶硅电介质保形地沉积在同一主机上或主机外部。

    INTEGRATED OXIDE AND SI ETCH FOR 3D CELL CHANNEL MOBILITY IMPROVEMENTS
    18.
    发明申请
    INTEGRATED OXIDE AND SI ETCH FOR 3D CELL CHANNEL MOBILITY IMPROVEMENTS 审中-公开
    一体化氧化物和SI ETCH用于3D细胞通道移动性改进

    公开(公告)号：US20160042968A1

    公开(公告)日：2016-02-11

    申请号：US14452328

    申请日：2014-08-05

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Nitin K. Ingle

    IPC: H01L21/311 ,  H01L21/3065 ,  H01L27/115 ,  H01L21/02

    CPC classification number: H01L21/31116 ,  H01L21/02068 ,  H01L21/3065 ,  H01L21/32135 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Methods of forming single crystal channel material in a 3-d flash memory cell using only gas-phase etching techniques are described. The methods include gas-phase etching native oxide from a polysilicon layer on a conformal ONO layer. The gas-phase etch also removes native oxide from the exposed single crystal silicon substrate the bottom of a 3-d flash memory hole. The polysilicon layer is removed, also with a gas-phase etch, on the same substrate processing mainframe. Both native oxide removal and polysilicon removal use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. Epitaxial silicon is then grown from the exposed single crystal silicon to create a high mobility replacement channel.

    Abstract translation: 描述了仅使用气相蚀刻技术在3-d闪存单元中形成单晶通道材料的方法。 这些方法包括从保形ONO层上的多晶硅层气相蚀刻天然氧化物。 气相蚀刻还从暴露的单晶硅衬底去除3-d闪存孔的底部的天然氧化物。 在相同的基板处理主机上也去除多晶硅层，同时也进行气相蚀刻。 天然氧化物去除和多晶硅去除都使用连接在同一主机上的远程激发的含氟装置，以便于在没有中间大气暴露的情况下进行这两种操作。 然后从暴露的单晶硅生长外延硅，以产生高迁移率替代通道。

    INTEGRATED OXIDE RECESS AND FLOATING GATE FIN TRIMMING
    19.
    发明申请
    INTEGRATED OXIDE RECESS AND FLOATING GATE FIN TRIMMING 有权
    一体化氧化物回流和浮动浇口熔融修整

    公开(公告)号：US20160035586A1

    公开(公告)日：2016-02-04

    申请号：US14448901

    申请日：2014-07-31

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Shankar Venkataraman ,  Nitin K. Ingle

    IPC: H01L21/3213 ,  H01L21/677 ,  H01L29/423 ,  H01L21/28 ,  H01L29/40

    CPC classification number: H01L21/32137 ,  H01J37/32357 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/67739 ,  H01L21/76224 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/66825

    Abstract: Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.

    Abstract translation: 描述了在不破坏真空的情况下回蚀浅沟槽隔离（STI）电介质和修整暴露的浮动栅极的方法。 这些方法包括凹陷氧化硅电介质间隙填充以暴露多晶硅浮动栅极的垂直侧壁。 然后对暴露的垂直侧壁进行各向同性蚀刻，以在相同的基板处理主机上均匀地稀薄多晶硅浮动栅极。 凹陷硅氧化物和各向同性蚀刻多晶硅都使用连接在同一主机上的远程激发的含氟设备，以便于在没有中间大气暴露的情况下进行两种操作。 然后可将多晶硅电介质保形地沉积在同一主机上或主机外部。

    Metal air gap
    20.
    发明授权
    Metal air gap 有权
    金属气隙

    公开(公告)号：US09159606B1

    公开(公告)日：2015-10-13

    申请号：US14448591

    申请日：2014-07-31

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Nitin K. Ingle

    IPC: H01L21/76 ,  H01L21/768 ,  H01L29/06

    CPC classification number: H01L21/7682 ,  H01J37/32357 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76882 ,  H01L29/0649

    Abstract: Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The air gaps may be located between copper lines on the same layer. A sacrificial patterned dielectric layer is used as a template to form a layer of copper by physical vapor deposition in a substrate processing system (i.e. a mainframe). Without breaking vacuum, the copper is redistributed into the gaps with a copper reflow process. Dielectric material from the template is removed, again in the same mainframe, using a remote fluorine etch process leaving the gapfill copper as the structural material. A conformal capping layer (such as silicon carbon nitride) is then deposited (e.g. by ALD) to seal the patterned substrate before removing the patterned substrate from the mainframe.

    Abstract translation: 描述了用于在图案化基板上的相邻铜线之间形成“气隙”的方法。 气隙可以位于同一层上的铜线之间。 牺牲图案化电介质层用作模板以通过物理气相沉积在基板处理系统（即，主机）中形成铜层。 在不破坏真空的情况下，铜通过铜回流工艺重新分配到间隙中。 使用远程氟蚀刻工艺，再次在相同的主机中除去来自模板的电介质材料，留下间隙填充铜作为结构材料。 然后在从主机移除图案化的衬底之前沉积保形覆盖层（例如氮化碳氮化物）（例如通过ALD）以密封图案化衬底。

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