公开(公告)号：US10319739B2

公开(公告)日：2019-06-11

申请号：US15882454

申请日：2018-01-29

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/67 ,  H01L29/10 ,  H01L21/308 ,  H01L21/28

Abstract: Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.

公开(公告)号：US09449846B2

公开(公告)日：2016-09-20

申请号：US14607883

申请日：2015-01-28

Applicant: Applied Materials, Inc.

Inventor： Jie Liu ,  Vinod R. Purayath ,  Xikun Wang ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/302 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/115

CPC classification number: H01L21/32136 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32954 ,  H01L21/32135 ,  H01L21/823437 ,  H01L27/11582

Abstract: Methods of selectively etching tungsten from the surface of a patterned substrate are described. The methods electrically separate vertically arranged tungsten slabs from one another as needed. The vertically arranged tungsten slabs may form the walls of a trench during manufacture of a vertical flash memory cell. The tungsten etch may selectively remove tungsten relative to films such as silicon, polysilicon, silicon oxide, aluminum oxide, titanium nitride and silicon nitride. The methods include exposing electrically-shorted tungsten slabs to remotely-excited fluorine formed in a remote plasma region. Process parameters are provided which result in uniform tungsten recess within the trench. A low electron temperature is maintained in the substrate processing region to achieve high etch selectivity and uniform removal throughout the trench.

Abstract translation: 描述了从图案化衬底的表面选择性地蚀刻钨的方法。 所述方法根据需要将垂直排列的钨板彼此电分离。 在垂直闪存单元的制造期间，垂直布置的钨板可以形成沟槽的壁。 钨蚀刻可以相对于诸如硅，多晶硅，氧化硅，氧化铝，氮化钛和氮化硅的膜选择性地去除钨。 这些方法包括将电短路钨板暴露于在远程等离子体区域中形成的远程激发的氟。 提供了在沟槽内产生均匀的钨凹槽的工艺参数。 在基板处理区域中保持低电子温度，以实现高蚀刻选择性并且在整个沟槽中均匀地去除。

公开(公告)号：US09396989B2

公开(公告)日：2016-07-19

申请号：US14164874

申请日：2014-01-27

Applicant: APPLIED MATERIALS, INC.

Inventor： Vinod R. Purayath ,  Nitin K. Ingle

IPC: H01L21/311 ,  H01B13/00 ,  B44C1/22 ,  B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  H01L21/768 ,  H01L21/762 ,  H01L27/108 ,  H01L21/3065 ,  C23C2/00 ,  H01J37/32

CPC classification number: H01L21/7682 ,  C23C2/006 ,  H01J37/32357 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/76205 ,  H01L27/1087 ,  H01L2221/101

Abstract: Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The common name “air gap” will be used interchangeably the more technically accurate “gas pocket” and both reflect a variety of pressures and elemental ratios. The gas pockets may be one or more pores within dielectric material located between copper lines. Adjacent copper lines may be bordered by a lining layer and air gaps may extend from one lining layer on one copper line to the lining layer of an adjacent copper line. The gas pockets can have a dielectric constant approaching one, favorably reducing interconnect capacitance compared with typical low-K dielectric materials.

Abstract translation: 描述了用于在图案化基板上的相邻铜线之间形成“气隙”的方法。 通用名称“气隙”可以互换使用更技术上更精确的“气袋”，并且都反映了各种压力和元素比。 气穴可以是位于铜线之间的电介质材料内的一个或多个孔。 相邻的铜线可以由衬里层界定，并且气隙可以从一条铜线上的一个衬里层延伸到相邻铜线的衬里层。 与典型的低K电介质材料相比，气穴可以具有接近一个的介电常数，有利地减小互连电容。

公开(公告)号：US09165786B1

公开(公告)日：2015-10-20

申请号：US14452220

申请日：2014-08-05

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Nitin K. Ingle

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/67

CPC classification number: H01L21/31116 ,  H01L21/67207 ,  H01L28/00 ,  H01L29/66833

Abstract: Methods of etching back an oxide-nitride-oxide (ONO) layer of a 3-d flash memory cell without breaking vacuum are described. The methods include recessing the two outer silicon oxide dielectric layers to expose the flanks of the thin silicon nitride layer. The silicon nitride layer is then etched back from all exposed sides to hasten the process on the same substrate processing mainframe. Both etching back the silicon oxide and etching back the silicon nitride use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The process may also be reversed such that the silicon nitride is etched back first.

Abstract translation: 描述了在不破坏真空的情况下将3-d闪存单元的氧化物 - 氮化物 - 氧化物（ONO）层刻蚀的方法。 这些方法包括使两个外部氧化硅介电层凹陷以暴露薄氮化硅层的侧面。 然后从所有暴露的侧面回蚀刻氮化硅层，以加速相同基板处理主机上的工艺。 两者都蚀刻氧化硅并且将附着在相同主机上的远程激发的含氟设备的氮化硅用途蚀刻回来，以便于在没有中间大气暴露的情况下执行这两种操作。 该方法也可以颠倒，使得首先蚀刻氮化硅。

公开(公告)号：US20150214092A1

公开(公告)日：2015-07-30

申请号：US14164874

申请日：2014-01-27

Applicant: APPLIED MATERIALS, INC.

Inventor： Vinod R. Purayath ,  Nitin K. Ingle

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/7682 ,  C23C2/006 ,  H01J37/32357 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/76205 ,  H01L27/1087 ,  H01L2221/101

Abstract: Methods are described for forming “air gaps” between adjacent copper lines on patterned substrates. The common name “air gap” will be used interchangeably the more technically accurate “gas pocket” and both reflect a variety of pressures and elemental ratios. The gas pockets may be one or more pores within dielectric material located between copper lines. Adjacent copper lines may be bordered by a lining layer and air gaps may extend from one lining layer on one copper line to the lining layer of an adjacent copper line. The gas pockets can have a dielectric constant approaching one, favorably reducing interconnect capacitance compared with typical low-K dielectric materials.

Abstract translation: 描述了用于在图案化基板上的相邻铜线之间形成“气隙”的方法。 通用名称“气隙”可以互换使用更技术上更精确的“气袋”，并且都反映了各种压力和元素比。 气穴可以是位于铜线之间的电介质材料内的一个或多个孔。 相邻的铜线可以由衬里层界定，并且气隙可以从一条铜线上的一个衬里层延伸到相邻铜线的衬里层。 与典型的低K电介质材料相比，气穴可以具有接近一个的介电常数，有利地减小互连电容。

公开(公告)号：US09496167B2

公开(公告)日：2016-11-15

申请号：US14448059

申请日：2014-07-31

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Shankar Venkataraman ,  Nitin K. Ingle

IPC: H01L21/764 ,  H01L27/115 ,  H01L21/311 ,  H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01J37/32357 ,  H01L21/02071 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/68764 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66833 ,  H01L29/7887

Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Abstract translation: 描述形成闪速存储器单元的方法，其包括用于改善性能的气隙。 这些方法对于所谓的“2-d平坦单元”闪存架构是有用的。 2-d平板电池闪存包括反应离子蚀刻，以将沟槽挖掘成包含高功函数和其它金属层的多层。 本文描述的方法从多层沟槽的侧壁去除金属氧化物碎屑，然后在不破坏真空的情况下选择性地去除成为气隙的浅沟槽隔离（STI）氧化。 金属氧化物去除和STI氧化去除都是使用远程激发的氟等离子体流出物，在相同的主机中进行高选择性蚀刻工艺。

公开(公告)号：US20160218018A1

公开(公告)日：2016-07-28

申请号：US14607883

申请日：2015-01-28

Applicant: Applied Materials, Inc.

Inventor： Jie Liu ,  Vinod R. Purayath ,  Xikun Wang ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/3213 ,  H01L27/115 ,  H01L21/8234

CPC classification number: H01L21/32136 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32954 ,  H01L21/32135 ,  H01L21/823437 ,  H01L27/11582

Abstract: Methods of selectively etching tungsten from the surface of a patterned substrate are described. The methods electrically separate vertically arranged tungsten slabs from one another as needed. The vertically arranged tungsten slabs may form the walls of a trench during manufacture of a vertical flash memory cell. The tungsten etch may selectively remove tungsten relative to films such as silicon, polysilicon, silicon oxide, aluminum oxide, titanium nitride and silicon nitride. The methods include exposing electrically-shorted tungsten slabs to remotely-excited fluorine formed in a remote plasma region. Process parameters are provided which result in uniform tungsten recess within the trench. A low electron temperature is maintained in the substrate processing region to achieve high etch selectivity and uniform removal throughout the trench.

Abstract translation: 描述了从图案化衬底的表面选择性地蚀刻钨的方法。 所述方法根据需要将垂直排列的钨板彼此电分离。 在垂直闪存单元的制造期间，垂直布置的钨板可以形成沟槽的壁。 钨蚀刻可以相对于诸如硅，多晶硅，氧化硅，氧化铝，氮化钛和氮化硅的膜选择性地去除钨。 这些方法包括将电短路钨板暴露于在远程等离子体区域中形成的远程激发的氟。 提供了在沟槽内产生均匀的钨凹槽的工艺参数。 在基板处理区域中保持低电子温度，以实现高蚀刻选择性并且在整个沟槽中均匀地去除。

公开(公告)号：US09263278B2

公开(公告)日：2016-02-16

申请号：US14230590

申请日：2014-03-31

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/3065 ,  H01J37/00 ,  H01L21/28 ,  H01L21/3213 ,  H01J37/32

CPC classification number: H01L21/28273 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/32137

Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

Abstract translation: 描述了以两种不同蚀刻速率蚀刻两个掺杂硅部分的方法。 当两者都暴露并存在于相同的衬底上时，可以比p型硅部分蚀刻n型硅部分。 n型硅部分可以掺杂磷，并且p型硅部分可以掺杂硼。 在一个示例中，n型硅部分是单晶硅，p型硅部分是多晶硅（即多晶硅）。 p型硅部分可以是闪存单元中的多晶硅浮动栅极，并且可以位于栅极氧化硅的上方，栅极氧化硅又位于n型有源区单晶硅部分之上。 n型有源区硅部分的额外修整可以减少使用期间被捕获的电荷的积累并且增加闪存器件的寿命。

公开(公告)号：US20150270366A1

公开(公告)日：2015-09-24

申请号：US14222418

申请日：2014-03-21

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Nitin K. Ingle

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/49 ,  H01L29/788

CPC classification number: H01L29/515 ,  H01J37/32357 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/788

Abstract: Flash memory cells and methods of formation are described for flash memory cells having air gaps through which electrons may pass to alter the charge state of the floating gate. A dummy gate is initially deposited and a polysilicon gate is deposited on the dummy gate. A silicon oxide film is then deposited on the sides of the active area, the dummy gate and the polysilicon. The silicon oxide film holds the polysilicon in place while the dummy gate is selectively etched away. The dummy gate may be doped to increase etch rate. Formerly, silicon oxide was used as a dielectric barrier through which electrons were passed to charge and discharge the floating gate (polysilicon). Eliminating material in the dielectric barrier reduces the tendency to accumulate trapped charges during use and increase the lifespan of flash memory devices.

Abstract translation: 对具有气隙的闪存单元描述闪存单元和形成方法，电子可通过该空隙来改变浮动栅极的电荷状态。 最初沉积一个虚拟栅极，并在该虚拟栅极上沉积多晶硅栅极。 然后在有源区域，伪栅极和多晶硅的侧面上沉积氧化硅膜。 氧化硅膜将多晶硅保持就位，同时选择性地蚀刻掉虚拟栅极。 伪栅极可以被掺杂以增加蚀刻速率。 以前，使用氧化硅作为电子通过电介质势垒来对浮栅（多晶硅）进行充电和放电。 在介质屏障中消除材料减少了在使用过程中累积陷阱电荷的趋势，并增加了闪存器件的使用寿命。

公开(公告)号：US20150170920A1

公开(公告)日：2015-06-18

申请号：US14230590

申请日：2014-03-31

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/3065

CPC classification number: H01L21/28273 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/32137

Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

Abstract translation: 描述了以两种不同蚀刻速率蚀刻两个掺杂硅部分的方法。 当两者都暴露并存在于相同的衬底上时，可以比p型硅部分蚀刻n型硅部分。 n型硅部分可以掺杂磷，并且p型硅部分可以掺杂硼。 在一个示例中，n型硅部分是单晶硅，p型硅部分是多晶硅（即多晶硅）。 p型硅部分可以是闪存单元中的多晶硅浮动栅极，并且可以位于栅极氧化硅的上方，栅极氧化硅又位于n型有源区单晶硅部分之上。 n型有源区硅部分的额外修整可以减少使用期间被捕获的电荷的累积并且增加闪存器件的寿命。