公开(公告)号：US20250028531A1

公开(公告)日：2025-01-23

申请号：US18353345

申请日：2023-07-17

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Yasuo ISHII ,  Joseph Michael PUSDESRIS

IPC: G06F9/30 ,  G06F13/16

Abstract: Processing circuitry to execute load operations, each associated with an identifier. Prediction circuitry to receive a given load value associated with a given identifier, and to make, in dependence on the given load value, a prediction indicating a predicted load value for a subsequent load operation to be executed by the processing circuitry and an ID-delta value indicating a difference between the given identifier and an identifier of the subsequent load operation. The predicted load value being predicted in dependence on at least one occurrence of each of the given load value and the predicted load value during execution of a previously-executed sequence of load operations. The prediction circuitry is configured to determine the ID-delta value in dependence on a difference between identifiers associated with the at least one occurrence of each of the given load value and the predicted load value in the previously-executed sequence of load operations.

公开(公告)号：US20230176979A1

公开(公告)日：2023-06-08

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Joseph Michael PUSDESRIS ,  . ABHISHEK RAJA ,  Karthik SUNDARAM ,  Anoop Ramachandra IYER ,  Michael Brian SCHINZLER ,  James David DUNDAS ,  Yasuo ISHII

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.

公开(公告)号：US20230120596A1

公开(公告)日：2023-04-20

申请号：US17505854

申请日：2021-10-20

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Nicholas Andrew PLANTE ,  Yasuo ISHII ,  Chris ABERNATHY

IPC: G06F9/38 ,  G06F9/30

Abstract: A predicated-loop-terminating branch instruction controls, based on whether a loop termination condition is satisfied, whether the processing circuitry should process a further iteration of a predicated loop body or process a following instruction. If at least one unnecessary iteration of the predicated loop body is processed following a mispredicted-non-termination branch misprediction when the loop termination condition is mispredicted as unsatisfied for a given iteration when it should have been satisfied, processing of the at least one unnecessary iteration of the predicated loop body is predicated to suppress an effect of the at least one unnecessary iteration. When the mispredicted-non-termination branch misprediction is detected for the given iteration of the predicated-loop-terminating branch instruction, in response to determining that a flush suppressing condition is satisfied, flushing of the at least one unnecessary iteration of the predicated loop body is suppressed as a response to the mispredicted-non-termination branch misprediction.

公开(公告)号：US20220147459A1

公开(公告)日：2022-05-12

申请号：US17093792

申请日：2020-11-10

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Adrian MONTERO ,  Joseph Michael PUSDESRIS ,  Karthik SUNDARAM ,  Yasuo ISHII

IPC: G06F12/0862

Abstract: Data processing apparatuses and methods of processing data are disclosed. The operations comprise: storing copies of data items; and storing, in a producer pattern history table, a plurality of producer-consumer relationships, each defining an association between producer load indicator and a plurality of consumer load entries, each consumer load entry comprising a consumer load indicator and one or more usefulness metrics. Further steps comprise: initiating, in response to a data load from an address corresponding to the producer load indicator in the producer pattern history table and when at least one of the corresponding one or more usefulness meets a criterion, a producer prefetch of data to be prefetched for storing as a local copy; and issuing, when the data is returned, one or more consumer prefetches to return consumer data from a consumer address generated from the data returned by the producer prefetch and a consumer load indicator of a consumer load entry.

公开(公告)号：US20210271486A1

公开(公告)日：2021-09-02

申请号：US16806063

申请日：2020-03-02

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Joseph Michael PUSDESRIS ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50

Abstract: An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.

公开(公告)号：US20180293166A1

公开(公告)日：2018-10-11

申请号：US15479348

申请日：2017-04-05

Applicant: ARM Limited

Inventor： Michael FILIPPO ,  Klas Magnus BRUCE ,  Vasu KUDARAVALLI ,  Adam GEORGE ,  Muhammad Umar FAROOQ ,  Joseph Michael PUSDESRIS

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0815 ,  G06F11/10

CPC classification number: G06F12/0811 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/62

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.

公开(公告)号：US20230297384A1

公开(公告)日：2023-09-21

申请号：US17699326

申请日：2022-03-21

Applicant: Arm Limited

Inventor： Nicholas Andrew PLANTE ,  Joseph Michael PUSDESRIS ,  Jungsoo KIM

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30181 ,  G06F9/30079 ,  G06F9/30029

Abstract: A data processing apparatus is provided. Rename circuitry performs a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers. Each of the mappings is associated with an elimination field value. Operation elimination circuitry replaces an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set. Operation circuitry responds to a subsequent operation that accesses the destination register when the elimination field value is set; by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result.

公开(公告)号：US20230229596A1

公开(公告)日：2023-07-20

申请号：US17579842

申请日：2022-01-20

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Balaji VIJAYAN ,  Karthik SUNDARAM ,  Yasuo ISHII ,  Joseph Michael PUSDESRIS

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/602

Abstract: Indirect prefetch circuitry initiates a producer prefetch requesting return of producer data having a producer address and at least one consumer prefetch to request prefetching of consumer data having a consumer address derived from the producer data. A producer prefetch filter table stores producer filter entries indicative of previous producer addresses of previous producer prefetches. Initiation of a requested producer prefetch for producer data having a requested producer address is suppressed when a lookup of the producer prefetch filter table determines that the requested producer address hits against a producer filter entry of the table. The lookup of the producer prefetch filter table for the requested producer address depends on a subset of bits of the requested producer address including at least one bit which distinguishes different chunks of data within a same cache line.

公开(公告)号：US20210357228A1

公开(公告)日：2021-11-18

申请号：US15930907

申请日：2020-05-13

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Joseph Michael PUSDESRIS ,  Adrian MONTERO ,  Balaji VIJAYAN

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/345

Abstract: An apparatus and method are provided. The apparatus comprises storage circuitry to store a plurality of data elements. Processing circuitry executes a stream of instructions comprising access instructions that access some of the data elements at given locations.
Training circuitry determines a pattern of the given locations based on the access instructions. Prefetch circuitry performs prefetches based on the pattern and filter circuitry filters the access instructions used by the training circuitry to determine the pattern by including discontinuous access instructions whose given location raises a discontinuity with the given location of a previous access instruction. In this way, it is possible to perform prefetching by calculating, rather than guessing, at a cumulative stride between the access instructions.

公开(公告)号：US20200073576A1

公开(公告)日：2020-03-05

申请号：US16118610

申请日：2018-08-31

Applicant: Arm Limited

Inventor： Adrian MONTERO ,  Miles Robert DOOLEY ,  Joseph Michael PUSDESRIS ,  Klas Magnus BRUCE ,  Chris ABERNATHY

IPC: G06F3/06 ,  G11B19/04 ,  G06F9/50 ,  G06F12/0862

Abstract: Storage circuitry is provided, that is designed to form part of a memory hierarchy. The storage circuitry comprises receiver circuitry for receiving a request to obtain data from the memory hierarchy. Transfer circuitry causes the data to be stored at a selected destination in response to the request, wherein the selected destination is selected in dependence on at least one selection condition. Tracker circuitry tracks the request while the request is unresolved. If at least one selection condition is met then the destination is the storage circuitry and otherwise the destination is other storage circuitry in the memory hierarchy.