公开(公告)号：US09928195B2

公开(公告)日：2018-03-27

申请号：US14959170

申请日：2015-12-04

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Peter Andrew Riocreux ,  Sean James Salisbury ,  Daniel Adam Sara ,  George Robert Scott Lloyd

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  G06F13/364 ,  G06F12/0815 ,  G06F13/40

CPC classification number: G06F13/364 ,  G06F12/0815 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/621

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.

公开(公告)号：US09507716B2

公开(公告)日：2016-11-29

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Jamshed Jalal ,  Mark David Werkheiser ,  Arthur Laughton ,  George Robert Scott Lloyd ,  Peter Andrew Riocreux ,  Daniel Sara

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。

公开(公告)号：US20240055047A1

公开(公告)日：2024-02-15

申请号：US17885709

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Edward Martin McCombs, JR. ,  Andrew David Tune ,  Sean James Salisbury ,  Rahul Mathur ,  Hsin-Yu Chen ,  Phani Raja Bhushan Chalasani

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

公开(公告)号：US20240054073A1

公开(公告)日：2024-02-15

申请号：US17885780

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, JR.

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

公开(公告)号：US11023390B1

公开(公告)日：2021-06-01

申请号：US16831975

申请日：2020-03-27

Applicant: Arm Limited

Inventor： Eduard Vardanyan ,  Sean James Salisbury

IPC: G06F13/14

Abstract: Resizing circuitry comprises at least one buffer having buffer entries each corresponding to one of at least two shift registers, each shift register comprising storage circuits connected in a ring to transfer a token bit between storage circuits. Selection circuitry controls, based on the shift registers, writing of data sections of input data units having a first number of data sections to the buffer(s), to form output data units having a second number of data sections. For a given buffer entry corresponding to a given shift register, depending on whether the token bit is stored in a first or second subset of storage circuits, the selection circuitry controls writing of a selected data section of a received input data unit to the given buffer entry or prevents overwriting of the given buffer entry. At least two of the shift registers have different relative arrangements of the first and second subsets of storage circuits.

公开(公告)号：US10942878B1

公开(公告)日：2021-03-09

申请号：US16831266

申请日：2020-03-26

Applicant: Arm Limited

Inventor： Sean James Salisbury ,  Chiranjeev Acharya ,  Eduard Vardanyan ,  Premkishore Shivakumar

IPC: G06F13/28 ,  G06F9/46

Abstract: An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.

公开(公告)号：US10740032B2

公开(公告)日：2020-08-11

申请号：US16148295

申请日：2018-10-01

Applicant: Arm Limited

Inventor： Chiranjeev Acharya ,  Sean James Salisbury ,  Eduard Vardanyan ,  Arthur Brian Laughton

IPC: G06F3/06 ,  G06F9/52 ,  G06F30/30 ,  G06F119/18

Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.

公开(公告)号：US10255103B2

公开(公告)日：2019-04-09

申请号：US15478443

申请日：2017-04-04

Applicant: ARM Limited

Inventor： Chiranjeev Acharya ,  Arthur Brian Laughton ,  Sean James Salisbury

IPC: G06F9/46 ,  G06F13/364 ,  G06F13/16 ,  G06F13/42 ,  G06F5/14

Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.

公开(公告)号：US20250068563A1

公开(公告)日：2025-02-27

申请号：US18947239

申请日：2024-11-14

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, JR.

IPC: G06F12/0802

Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

公开(公告)号：US11599467B2

公开(公告)日：2023-03-07

申请号：US17331806

申请日：2021-05-27

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Bruce James Mathewson ,  Tushar P Ringe ,  Sean James Salisbury ,  Antony John Harris

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0895

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.