公开(公告)号：US09317096B2

公开(公告)日：2016-04-19

申请号：US13717992

申请日：2012-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Bircher ,  Madhu Saravana Sibi Govindan ,  Brian E. Waldecker

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203

Abstract: Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold.

Abstract translation: 提供方法，系统和媒体用于电源管理。 电源管理包括但不限于在计算机系统中将取消的条目的历史记录到中断从单位从活动模式转换到低功率状态的低功率状态，并且禁止将单元转换到低电平状态 当由取消的条目的历史指示的许多取消的条目超过取消的入口阈值时，电源状态。

公开(公告)号：US20150185801A1

公开(公告)日：2015-07-02

申请号：US14146591

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

Abstract translation: 电源选通决定可以基于缓存污垢的测量。 分析器逻辑可以基于与组件相关联的一个或多个高速缓存的高速缓存污垢来选择性地加电处理系统的组件。 当高速缓存污物超过阈值时，分析器逻辑可以对组件供电，并且当高速缓存污垢不超过阈值时，分析器逻辑可以维持组件处于空闲状态。 空闲时间预测逻辑可以用于预测组件的空闲时间的持续时间。 然后，分析器逻辑可以基于高速缓存污物和预测的空闲时间选择性地对组件进行加电。

公开(公告)号：US20140181556A1

公开(公告)日：2014-06-26

申请号：US13724599

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L. Bircher ,  Mahdu S.S. Govindan ,  Michael J. Schulte ,  Manish Arora

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.

Abstract translation: 公开了一种基于先前预测退出低功率状态的方法和装置。 集成电路（IC）包括功能单元，其被配置为在操作期间在活动状态的间隔和空闲状态的间隔之间循环。 IC还包括电源管理单元，其被配置为响应于功能单元进入空闲状态而将功能单元置于低功率状态。 电源管理单元还被配置为在进入低功率之后的预定时间，预先使功能单元退出低功率状态。 预定时间基于在进入低功率状态之前进行的空闲状态持续时间的预测。 预测可以由预测单元基于功能单元处于空闲状态的间隔的持续时间的历史来生成。

公开(公告)号：US20140181553A1

公开(公告)日：2014-06-26

申请号：US13723868

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L. Bircher ,  Mahdu S.S. Govindan ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/329 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for idle phase prediction in integrated circuits is disclosed. In one embodiment, an integrated circuit (IC) includes a functional unit configured to cycle between intervals of an active state and an idle state. The IC further includes a prediction unit configured to record a history of idle state durations for a plurality of intervals of the idle state. Based on the history of idle state durations, the prediction unit is configured to generate a prediction of the duration of the next interval of the idle state. The prediction may be used by a power management unit to, among other uses, determine whether to place the functional unit in a low power (e.g., sleep) state.

Abstract translation: 公开了一种用于集成电路中的空闲相位预测的方法和装置。 在一个实施例中，集成电路（IC）包括被配置为在活动状态的间隔和空闲状态之间循环的功能单元。 IC还包括：预测单元，被配置为在空闲状态的多个间隔中记录空闲状态持续时间的历史。 基于空闲状态持续时间的历史，预测单元被配置为生成空闲状态的下一个间隔的持续时间的预测。 电力管理单元可以使用该预测，除了其他用途之外，确定是否将功能单元置于低功率（例如睡眠）状态。

公开(公告)号：US20140149772A1

公开(公告)日：2014-05-29

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。