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    ALTERNATIVE PROTOCOL OVER PHYSICAL LAYER
    11.
    发明公开
    ALTERNATIVE PROTOCOL OVER PHYSICAL LAYER 审中-公开

    公开(公告)号：US20230342325A1

    公开(公告)日：2023-10-26

    申请号：US18216908

    申请日：2023-06-30

    Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

    Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

    IPC: G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/4282 ,  G06F13/1689 ,  G06F2213/0026

    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

    Alternative protocol over physical layer
    12.
    发明授权
    Alternative protocol over physical layer 有权

    公开(公告)号：US11693813B2

    公开(公告)日：2023-07-04

    申请号：US16427020

    申请日：2019-05-30

    Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

    Inventor： Gordon Caruk ,  Maurice B. Steinman ,  Gerald R. Talbot ,  Joseph D. Macri

    IPC: G06F13/20 ,  G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/4282 ,  G06F13/1689 ,  G06F2213/0026

    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

    DATA COMMUNICATIONS WITH ENHANCED SPEED MODE
    13.
    发明申请
    DATA COMMUNICATIONS WITH ENHANCED SPEED MODE 有权

    公开(公告)号：US20220035765A1

    公开(公告)日：2022-02-03

    申请号：US17503959

    申请日：2021-10-18

    Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

    Inventor： Gordon Caruk ,  Gerald R. Talbot

    IPC: G06F13/42 ,  G06F13/12 ,  G06F13/40

    Abstract: An interconnect controller for a data processing platform includes a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer, and a physical layer controller coupled to the data link layer controller and adapted to be coupled to a communication link. The physical layer controller operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount. In response to performing a link initialization, the interconnect controller performs at least one setup operation to select a speed, and subsequently operates the communication link using a selected speed.

    Data communications with enhanced speed mode
    14.
    发明授权
    Data communications with enhanced speed mode 有权

    公开(公告)号：US11151075B2

    公开(公告)日：2021-10-19

    申请号：US16221181

    申请日：2018-12-14

    Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

    Inventor： Gordon Caruk ,  Gerald R. Talbot

    IPC: G06F13/42 ,  G06F13/12 ,  G06F13/40

    Abstract: An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.

    SELECTIVE INSERTION OF CLOCK MISMATCH COMPENSATION SYMBOLS IN SIGNAL TRANSMISSIONS
    17.
    发明申请
    SELECTIVE INSERTION OF CLOCK MISMATCH COMPENSATION SYMBOLS IN SIGNAL TRANSMISSIONS 有权
    信号传输中时钟误差补偿符号的选择性插入

    公开(公告)号：US20140129867A1

    公开(公告)日：2014-05-08

    申请号：US13670086

    申请日：2012-11-06

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gordon F. Caruk ,  Gerald R. Talbot

    IPC: G06F1/00

    CPC classification number: G06F1/00 ,  G06F1/04 ,  G06F5/06 ,  H04L7/00 ,  H04L7/005 ,  H04L2007/045

    Abstract: In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device having capability to compensate for a clock frequency mismatch. A device includes an interconnect interface comprising a transmit port and a receive port, and a configuration structure. The configuration structure comprises a capability field to store a value indicating whether the device has a capability to compensate for a clock frequency mismatch, and an enable field. The device further includes a packet control module to configure a rate of insertion of clock mismatch compensation symbols by the transmit port into a data stream responsive to a value stored at the enable field.

    Abstract translation: 在包括通过互连耦合的第一设备和第二设备的系统中，一种方法包括将响应于第二设备的多个插入速率的第一设备的发送端口的时钟失配补偿符号的插入速率设置为 器件具有补偿时钟频率不匹配的能力。 一种设备包括包括发送端口和接收端口的互连接口以及配置结构。 配置结构包括存储指示设备是否具有补偿时钟频率失配的能力的值的能力字段和启用字段。 该设备还包括分组控制模块，用于响应于存储在启用字段的值，将发送端口的时钟失配补偿符号的速率配置成数据流。

    Periodic receiver clock data recovery with dynamic data edge
    18.
    发明授权
    Periodic receiver clock data recovery with dynamic data edge 有权

    公开(公告)号：US12174769B2

    公开(公告)日：2024-12-24

    申请号：US17705048

    申请日：2022-03-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gurunath Dollin ,  Edoardo Prete ,  Milam Paraschou ,  Edward Wade Thoenes ,  Ryan J. Hensley ,  Gerald R. Talbot

    IPC: G06F13/40 ,  G06F1/08 ,  G06F1/12 ,  G06F13/42 ,  H03K19/173

    Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.

    THREE-STAGE DIFFERENTIAL RING OSCILLATOR GENERATING DIFFERENTIAL IN-PHASE AND QUADRATURE-PHASE CLOCKS
    19.
    发明公开
    THREE-STAGE DIFFERENTIAL RING OSCILLATOR GENERATING DIFFERENTIAL IN-PHASE AND QUADRATURE-PHASE CLOCKS 审中-公开

    公开(公告)号：US20230396240A1

    公开(公告)日：2023-12-07

    申请号：US17831013

    申请日：2022-06-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Thomas H. Likens ,  Gerald R. Talbot

    IPC: H03K3/03 ,  G06F1/06

    CPC classification number: H03K3/0322 ,  G06F1/06

    Abstract: A three-stage differential ring oscillator circuit has a first differential stage, a second differential stage, and a third differential stage and generates six phases (two in each stage) used to form differential in-phase and quadrature-phase clock signals. A cross coupled inverter pair couples the first stage output signals. A second cross coupled inverter pair couples the second stage output signals. A third cross coupled inverter pair couples the third stage output signals. A first interpolator generates a first quadrature-phase clock signal using two phases (one from the positive portion of the second stage and one from the negative portion of the third stage) and a second interpolator generates a second quadrature-phase clock signal using two phases (one from the negative portion of the second stage and one from the positive portion of the third stage). Two phases from the first differential stage form the differential pair of in-phase clock signals.

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