公开(公告)号：US20180068962A1

公开(公告)日：2018-03-08

申请号：US15649474

申请日：2017-07-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuang-Hsiung CHEN ,  Yu-Hsuan TSAI ,  Yu-Ying LEE ,  Sheng-Ming WANG ,  Wun-Jheng SYU

IPC: H01L23/00 ,  B81B7/00 ,  B81C1/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/02 ,  B81B7/0006 ,  B81B2207/012 ,  B81C1/0023 ,  B81C1/00333 ,  B81C2203/0792 ,  H01L21/563 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02373 ,  H01L2224/11462 ,  H01L2224/13018

Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).

公开(公告)号：US20170330870A1

公开(公告)日：2017-11-16

申请号：US15453656

申请日：2017-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Yu-Tzu PENG

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05582 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/24246 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H05K1/144 ,  H05K3/284 ,  H05K2203/1316

Abstract: A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

公开(公告)号：US20210091006A1

公开(公告)日：2021-03-25

申请号：US17109111

申请日：2020-12-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming WANG ,  Tien-Szu CHEN ,  Wen-Chih SHEN ,  Hsing-Wen LEE ,  Hsiang-Ming FENG

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L23/66 ,  H01L23/367 ,  H01P3/06 ,  H01L21/683

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

公开(公告)号：US20190198469A1

公开(公告)日：2019-06-27

申请号：US16293606

申请日：2019-03-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuang-Hsiung CHEN ,  Yu-Hsuan TSAI ,  Yu-Ying LEE ,  Sheng-Ming WANG ,  Wun-Jheng SYU

IPC: H01L23/00 ,  B81C1/00 ,  H01L25/00 ,  H01L25/065 ,  B81B7/00 ,  H01L21/56 ,  H01L23/31

Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.

公开(公告)号：US20180145037A1

公开(公告)日：2018-05-24

申请号：US15873784

申请日：2018-01-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

公开(公告)号：US20160240462A1

公开(公告)日：2016-08-18

申请号：US14624388

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

Abstract translation: 本公开涉及一种半导体衬底结构，半导体封装及其制造方法。 半导体衬底结构包括导电结构，电介质结构和金属凸块。 导电结构具有第一导电表面和第二导电表面。 电介质结构具有第一电介质表面和第二电介质表面。 第一导电表面不从第一电介质表面突出。 第二导电表面从第二电介质表面凹陷。 金属凸块设置在电介质结构的电介质开口中，并且物理地和电连接到第二导电表面。 金属凸块具有凹面。

公开(公告)号：US20140327125A1

公开(公告)日：2014-11-06

申请号：US14268981

申请日：2014-05-02

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu CHEN ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/00 ,  H01L21/50

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

Abstract translation: 提供半导体封装结构及其制造方法。 所述制造方法包括：提供衬底条，所述衬底条包括多个衬底单元; 在所述多个基板单元上设置多个芯片; 将包装密封剂设置在所述衬底条上以封装所述芯片; 在所述包装密封剂的顶表面上形成耐翘曲层; 并且分割所述衬底条以分离所述多个衬底单元以进一步制造多个半导体封装结构，其中所述耐翘曲层由具有选定厚度的选定材料形成以使所述半导体封装结构的翘曲变化在 温度在25℃至260℃之间，以小于560微米。