公开(公告)号：US20230096703A1

公开(公告)日：2023-03-30

申请号：US17491220

申请日：2021-09-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ying LEE

IPC: H01L23/498 ,  H01L23/60 ,  H01L23/00

Abstract: An electronic package structure and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate, a conductive element, and a support structure. The substrate has a bottom surface and a lateral surface angled with the bottom surface. The conductive element is on the lateral surface of the substrate. The support structure is on the bottom surface of the substrate and configured to space the bottom surface from an external carrier. A lateral surface of the support structure is spaced apart from the lateral surface of the substrate by a first distance.

公开(公告)号：US20200350239A1

公开(公告)日：2020-11-05

申请号：US16932690

申请日：2020-07-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ying LEE

IPC: H01L23/498 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.

公开(公告)号：US20180068962A1

公开(公告)日：2018-03-08

申请号：US15649474

申请日：2017-07-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuang-Hsiung CHEN ,  Yu-Hsuan TSAI ,  Yu-Ying LEE ,  Sheng-Ming WANG ,  Wun-Jheng SYU

IPC: H01L23/00 ,  B81B7/00 ,  B81C1/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/02 ,  B81B7/0006 ,  B81B2207/012 ,  B81C1/0023 ,  B81C1/00333 ,  B81C2203/0792 ,  H01L21/563 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02373 ,  H01L2224/11462 ,  H01L2224/13018

Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).

公开(公告)号：US20170330870A1

公开(公告)日：2017-11-16

申请号：US15453656

申请日：2017-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Yu-Tzu PENG

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0218 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05582 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/24246 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H05K1/144 ,  H05K3/284 ,  H05K2203/1316

Abstract: A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

公开(公告)号：US20180233643A1

公开(公告)日：2018-08-16

申请号：US15860567

申请日：2018-01-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Yi WU ,  Lu-Ming LAI ,  Yu-Ying LEE ,  Yung-Yi CHANG

IPC: H01L33/62 ,  H01L33/48 ,  H01L33/60

Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.

公开(公告)号：US20160225708A1

公开(公告)日：2016-08-04

申请号：US15006306

申请日：2016-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Chun-Che LEE ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/288 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion. The first portion includes a bonding pad and one portion of a conductive trace, and the second portion includes another portion of the conductive trace. An upper surface of the first portion is not coplanar with an upper surface of the second portion. A semiconductor packaging structure includes the semiconductor substrate.

Abstract translation: 半导体衬底包括绝缘层和埋在绝缘层的表面上的导电电路层。 导电电路层包括第一部分和第二部分。 第一部分包括接合焊盘和导电迹线的一部分，并且第二部分包括导电迹线的另一部分。 第一部分的上表面不与第二部分的上表面共面。 半导体封装结构包括半导体衬底。

公开(公告)号：US20150318235A1

公开(公告)日：2015-11-05

申请号：US14704769

申请日：2015-05-05

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu CHEN ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/77

CPC classification number: H01L23/49816 ,  H01L21/4828 ,  H01L23/49503 ,  H01L23/49534 ,  H01L23/49582 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49861 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.

Abstract translation: 提供了基板，其半导体封装件及其制造方法。 衬底包括上电路层和下电路层，上电路层包括至少一个迹线和至少一个焊盘，下电路层包括至少一个迹线和至少一个焊盘，其中上电路的迹线 层和下层电路层的迹线不对齐。

公开(公告)号：US20220157742A1

公开(公告)日：2022-05-19

申请号：US16953255

申请日：2020-11-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ying LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion.

公开(公告)号：US20200259058A1

公开(公告)日：2020-08-13

申请号：US16862447

申请日：2020-04-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Yi WU ,  Lu-Ming LAI ,  Yu-Ying LEE ,  Yung-Yi CHANG

IPC: H01L33/62 ,  B81C1/00 ,  H01L33/48

Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.

公开(公告)号：US20180350626A1

公开(公告)日：2018-12-06

申请号：US16102527

申请日：2018-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Yu-Tzu PENG

IPC: H01L21/48 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.