公开(公告)号：US10157887B2

公开(公告)日：2018-12-18

申请号：US15454520

申请日：2017-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  I-Cheng Wang ,  Wun-Jheng Syu

IPC: H01L23/28 ,  H01L23/48 ,  H01L23/528 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29 ,  H01L23/24 ,  H01L25/00 ,  H01L21/48

Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.

公开(公告)号：US09224707B2

公开(公告)日：2015-12-29

申请号：US14509320

申请日：2014-10-08

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H05K3/40 ,  H01L23/13

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并从上电路层向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。

公开(公告)号：US20150021766A1

公开(公告)日：2015-01-22

申请号：US14509320

申请日：2014-10-08

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。

公开(公告)号：US10854550B2

公开(公告)日：2020-12-01

申请号：US16109272

申请日：2018-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming Wang ,  Tien-Szu Chen ,  Wen-Chih Shen ,  Hsing-Wen Lee ,  Hsiang-Ming Feng

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L23/66 ,  H01L23/367 ,  H01P3/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

公开(公告)号：US10515884B2

公开(公告)日：2019-12-24

申请号：US14624388

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

公开(公告)号：US10134683B2

公开(公告)日：2018-11-20

申请号：US15430355

申请日：2017-02-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  I-Cheng Wang ,  Wun-Jheng Syu ,  Yu-Tzu Peng

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/367 ,  H01L23/29 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.

公开(公告)号：US09437532B2

公开(公告)日：2016-09-06

申请号：US14971165

申请日：2015-12-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H05K3/40 ,  H01L21/027 ,  H01L23/31 ,  H01L23/13

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

公开(公告)号：US08866311B2

公开(公告)日：2014-10-21

申请号：US13624548

申请日：2012-09-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract translation: 衬底包括第一介电层，第一电路图案，多个柱和第二电路图案。 第一电介质层具有相对的第一和第二电介质表面。 第一电路图案嵌入在第一电介质层中并且限定多个弯曲迹线表面。 每个支柱具有适于制造外部电连接的外表面和与相应的一个轨迹表面邻接的弯曲基底表面。 第二电路图案在第一电介质层的第二电介质表面上并且电连接到第一电路图案。

公开(公告)号：US10573624B2

公开(公告)日：2020-02-25

申请号：US16194265

申请日：2018-11-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  I-Cheng Wang ,  Wun-Jheng Syu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/24 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.

公开(公告)号：US10332851B2

公开(公告)日：2019-06-25

申请号：US15630843

申请日：2017-06-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Chieh Yang ,  Sheng-Ming Wang ,  Tien-Szu Chen

IPC: H01L23/00

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.