公开(公告)号：US20230317589A1

公开(公告)日：2023-10-05

申请号：US17710647

申请日：2022-03-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ying Lee

IPC: H01L23/498 ,  H01L25/16 ,  H01L23/31 ,  H01L23/49 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L25/167 ,  H01L23/3157 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/81 ,  H01L21/56 ,  H01L24/32 ,  H01L24/05 ,  H01L2224/81801 ,  H01L2224/32145 ,  H01L2224/02379 ,  H01L2224/14177 ,  H01L24/14 ,  H01L2224/16145 ,  H01L24/16 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2924/014 ,  H01L2224/13083

Abstract: A package structure includes a first die, a second die, an encapsulant and at least one electrical contact. The first die has an active surface. The second die is disposed on the first die, and has an active surface and a backside surface opposite to the active surface. The active surface of the second die is closer to the active surface of the first die than the backside surface of the second die is. The encapsulant encapsulates the first die and the second die, and has a top surface far away from the active surface of the first die. The electrical contact is exposed from the top surface of the encapsulant and is configured for connecting at least one conductive wire.

公开(公告)号：US11211536B2

公开(公告)日：2021-12-28

申请号：US16862447

申请日：2020-04-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Yi Wu ,  Lu-Ming Lai ,  Yu-Ying Lee ,  Yung-Yi Chang

IPC: H01L33/62 ,  H01L33/48 ,  B81C1/00 ,  B81B7/00 ,  H01L33/60

Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.

公开(公告)号：US10734337B2

公开(公告)日：2020-08-04

申请号：US16293606

申请日：2019-03-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuang-Hsiung Chen ,  Yu-Hsuan Tsai ,  Yu-Ying Lee ,  Sheng-Ming Wang ,  Wun-Jheng Syu

IPC: H01L23/28 ,  H01L23/00 ,  B81C1/00 ,  B81B7/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.

公开(公告)号：US10224298B2

公开(公告)日：2019-03-05

申请号：US15649474

申请日：2017-07-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuang-Hsiung Chen ,  Yu-Hsuan Tsai ,  Yu-Ying Lee ,  Sheng-Ming Wang ,  Wun-Jheng Syu

IPC: H01L23/28 ,  H01L23/00 ,  B81B7/00 ,  B81C1/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).

公开(公告)号：US11469165B2

公开(公告)日：2022-10-11

申请号：US16932690

申请日：2020-07-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ying Lee

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.

公开(公告)号：US10515884B2

公开(公告)日：2019-12-24

申请号：US14624388

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

公开(公告)号：US10483196B2

公开(公告)日：2019-11-19

申请号：US15887780

申请日：2018-02-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ying Lee

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.

公开(公告)号：US09054118B2

公开(公告)日：2015-06-09

申请号：US14313046

申请日：2014-06-24

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Hsiang-Ming Feng ,  Bing-Yun Cheng

IPC: H01L21/56 ,  H01L23/34 ,  H01L23/433 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract translation: 制造半导体器件封装的方法的实施例包括散热器矩阵和衬底。 多个半导体器件附接到基板。 然后，在散热片基板和基板之间形成封装体，其中封装体封装半导体器件。 然后，形成多个第一切割槽，其中第一切割槽延伸穿过散热器矩阵并且部分地延伸到包装主体中。 然后，形成多个第二切割槽，其中第二切割槽延伸穿过基板并通过封装主体延伸到第一切割槽，从而将散热器矩阵和基板分离成多个单独的半导体器件封装。

公开(公告)号：US12033934B2

公开(公告)日：2024-07-09

申请号：US17710647

申请日：2022-03-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ying Lee

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49 ,  H01L25/16

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/32 ,  H01L24/81 ,  H01L25/167 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/02379 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/014

Abstract: A package structure includes a first die, a second die, an encapsulant and at least one electrical contact. The first die has an active surface. The second die is disposed on the first die, and has an active surface and a backside surface opposite to the active surface. The active surface of the second die is closer to the active surface of the first die than the backside surface of the second die is. The encapsulant encapsulates the first die and the second die, and has a top surface far away from the active surface of the first die. The electrical contact is exposed from the top surface of the encapsulant and is configured for connecting at least one conductive wire.

公开(公告)号：US20220123192A1

公开(公告)日：2022-04-21

申请号：US17564065

申请日：2021-12-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Yi Wu ,  Lu-Ming Lai ,  Yu-Ying Lee ,  Yung-Yi Chang

IPC: H01L33/62 ,  H01L33/48 ,  B81C1/00

Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.