公开(公告)号：US20190051590A1

公开(公告)日：2019-02-14

申请号：US15673239

申请日：2017-08-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jen-Kuang FANG ,  Wen-Long LU

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.

公开(公告)号：US20180174981A1

公开(公告)日：2018-06-21

申请号：US15382594

申请日：2016-12-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: A semiconductor package includes a substrate, a dielectric layer, at least one conductive pillar and an electrical device. The dielectric layer is disposed on the substrate and defines at least one through hole corresponding to the respective first pad of the substrate. The conductive pillar is disposed in the respective through hole. The conductive pillar includes a body portion and a cap portion. The body portion is physically connected to the cap portion, and the cap portion is electrically connected to the first pad. A maximum width of the cap portion is greater than a maximum width of the body portion. The electrical device is disposed on the dielectric layer and electrically connected to the body portion of the conductive pillar.

公开(公告)号：US20180174954A1

公开(公告)日：2018-06-21

申请号：US15387018

申请日：2016-12-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Ching Kuo HSU

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

Abstract: A wiring structure includes a main body, a first dielectric layer, a first circuit layer and a second dielectric layer. The first dielectric layer is disposed on the main body, and defines a plurality of first grooves and at least one receiving portion between two first grooves. The first circuit layer is disposed on the first dielectric layer, and includes at least one first conductive trace disposed on the receiving portion. A width of the first conductive trace is less than a width of the receiving portion. A second dielectric layer disposed on the first dielectric layer, and extends into the first grooves.

公开(公告)号：US20180076177A1

公开(公告)日：2018-03-15

申请号：US15815357

申请日：2017-11-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/564 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13082 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48229 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A method for manufacturing a semiconductor package structure includes: (a) disposing at least one semiconductor element on a conductive structure, wherein the conductive structure includes at least one insulation layer and at least one circuit layer; (b) disposing an encapsulant on the conductive structure to cover the semiconductor element; (c) attaching a supporting structure on the conductive structure to surround the semiconductor element; and (d) disposing an upper element on the encapsulant, wherein a coefficient of thermal expansion of the upper element is in a range of variation less than or equal to about ±20% of a coefficient of thermal expansion of the circuit layer, and a bending modulus of the upper element is in a range of variation less than or equal to about ±35% of a bending modulus of the circuit layer.

公开(公告)号：US20220148936A1

公开(公告)日：2022-05-12

申请号：US17092193

申请日：2020-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU

IPC: H01L23/31

Abstract: A package structure and a circuit layer structure are provided in the present disclosure. The package structure includes a wiring structure, a first electronic device, a second electronic device and at least one dummy trace. The wiring structure includes a plurality of interconnection traces. The first electronic device and the second electronic device are disposed on the wiring structure, and electrically connected to each other through the interconnection traces. The dummy trace is adjacent to the interconnection traces. A mechanical strength of the at least one dummy trace is less than a mechanical strength of one of the interconnection traces.

公开(公告)号：US20220068781A1

公开(公告)日：2022-03-03

申请号：US17006688

申请日：2020-08-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and a plurality of conductive through vias. The conductive structure includes a dielectric layer, a circuit layer in contact with the dielectric layer, a plurality of dam portions and an outer metal layer. The dam portions extend through the dielectric layer. The dam portion defines a through hole. The outer metal layer is disposed adjacent to a top surface of the dielectric layer and extends into the through hole of the dam portion. The conductive through vias are disposed in the through holes of the dam portions and electrically connecting the circuit layer.

公开(公告)号：US20210296267A1

公开(公告)日：2021-09-23

申请号：US16825713

申请日：2020-03-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jhao-Cheng CHEN ,  Huang-Hsien CHANG ,  Wen-Long LU ,  Shao Hsuan CHUANG ,  Ching-Ju CHEN ,  Tse-Chuan CHOU

IPC: H01L23/00

Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.

公开(公告)号：US20210202413A1

公开(公告)日：2021-07-01

申请号：US16732071

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Chang LEE ,  Wen-Long LU

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device package includes a first electronic component having a first surface and a second surface opposite the first surface. The semiconductor device package further includes a first pad disposed on the first surface of the first electronic component. The first pad has a first surface facing away from the first surface of the first electronic component, a second surface opposite the first surface of the first pad, and a lateral surface extended between the first surface of the first pad and the second surface of the first pad. The semiconductor device package further includes a second pad disposed on the first surface of the first pad. The second pad has a first surface facing away from the first surface of the first pad, a second surface opposite the first surface of the second pad, and a lateral surface extended between the first surface of the second pad and the second surface of the second pad. A width of the first surface of the second pad is greater than a width of the second surface of the second pad. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US20210202393A1

公开(公告)日：2021-07-01

申请号：US16732166

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU

IPC: H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

Abstract: A package structure includes a substrate, a first electronic component, a second electronic component, a third electronic component and a connection component. The substrate includes a first surface and a second surface opposite the first surface. The first electronic component is disposed at the substrate and has a first active surface exposed from the second surface of the substrate. The second electronic component includes a second active surface facing the first active surface of the first electronic component. The second active surface of the second electronic component is electrically connected to the first active surface of the first electronic component. The third electronic component includes a third active surface facing the first active face of the first electronic component. The connection component electrically connects the third active surface of the third electronic component to the first active surface of the first electronic component. The connection component has at least two bendings.

公开(公告)号：US20210125965A1

公开(公告)日：2021-04-29

申请号：US16663084

申请日：2019-10-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device package includes a dielectric layer and a patterned conductive layer disposed in the dielectric layer. The dielectric layer has a first surface, a second surface opposite the first surface, and a third surface extended from the first surface to the second surface. The semiconductor device package also includes a first electronic component in direct contact with the first surface of the dielectric layer and a first connection structure disposed between the first electronic component and the patterned conductive layer. A method of manufacturing a semiconductor device package is also disclosed.