公开(公告)号：US20210202413A1

公开(公告)日：2021-07-01

申请号：US16732071

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Chang LEE ,  Wen-Long LU

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device package includes a first electronic component having a first surface and a second surface opposite the first surface. The semiconductor device package further includes a first pad disposed on the first surface of the first electronic component. The first pad has a first surface facing away from the first surface of the first electronic component, a second surface opposite the first surface of the first pad, and a lateral surface extended between the first surface of the first pad and the second surface of the first pad. The semiconductor device package further includes a second pad disposed on the first surface of the first pad. The second pad has a first surface facing away from the first surface of the first pad, a second surface opposite the first surface of the second pad, and a lateral surface extended between the first surface of the second pad and the second surface of the second pad. A width of the first surface of the second pad is greater than a width of the second surface of the second pad. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US20190148325A1

公开(公告)日：2019-05-16

申请号：US15809674

申请日：2017-11-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Chi-Chang LEE

IPC: H01L23/00 ,  H01L21/683

Abstract: An electronic device includes a dielectric layer, a redistribution layer, a conductive structure, an insulating layer and a solder bump. The dielectric layer has a first surface and a second surface opposite to the first surface, and defines a through hole extending between the first surface and the second surface. The redistribution layer is disposed on the first surface of the dielectric layer and in the through hole. The conductive structure is disposed on the redistribution layer. The conductive structure includes an upper portion and a lower portion. The lower portion is disposed on the redistribution layer, and the upper portion is disposed on the lower portion. The insulating layer covers a portion of the redistribution layer and surrounds a first portion of the lower portion of the conductive structure. The solder bump covers a portion of the conductive structure.

公开(公告)号：US20190139708A1

公开(公告)日：2019-05-09

申请号：US15804463

申请日：2017-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Chang LEE ,  Wen-Long LU

IPC: H01G4/30 ,  H01G4/10 ,  H01G4/008 ,  H01G4/012 ,  H01G4/228

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/0085 ,  H01G4/012 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/224 ,  H01G4/228 ,  H01G4/232

Abstract: A capacitor structure includes a first conductive layer, a first insulation layer, a first dielectric layer and a second conductive layer. The first conductive layer includes a first conductive material. The first insulation layer is disposed adjacent to the first conductive layer in a same plane as the first conductive layer. The first dielectric layer is on the first conductive layer and the first insulation layer. The second conductive layer is on the first dielectric layer and includes a second conductive material. The first conductive material is different from the second conductive material.

公开(公告)号：US20190103227A1

公开(公告)日：2019-04-04

申请号：US15721263

申请日：2017-09-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Chi-Chang LEE

IPC: H01G4/33 ,  H01G4/12 ,  H01G4/38 ,  H01G4/228 ,  H01G4/224 ,  H01L27/01 ,  H01L49/02 ,  H01G4/012

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01G4/1254 ,  H01G4/224 ,  H01G4/228 ,  H01G4/385 ,  H01L27/016 ,  H01L28/91

Abstract: A capacitor structure is disclosed. The capacitor structure includes a substrate, and a first electrode disposed on the substrate, the first electrode including a conductive layer, a first conductive post electrically connected to the conductive layer and a second conductive post electrically connected to the conductive layer. The capacitor structure further includes a planarization layer disposed on and covering the first electrode, the planarization layer disposed in a space between the first conductive post and the second conductive post, a first dielectric layer disposed on the planarization layer and in the space between the first conductive post and the second conductive post, and a second electrode disposed on the first dielectric layer.

公开(公告)号：US20170207151A1

公开(公告)日：2017-07-20

申请号：US14995572

申请日：2016-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen-Long LU ,  Chi-Chang LEE ,  Wei-Min HSIAO ,  Yuan-Feng CHIANG

IPC: H01L23/495 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49572 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/147 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/81

Abstract: A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first surface and a second surface opposite the first surface. The semiconductor elements are disposed on and electrically connected to the first surface of the conductive structure. The encapsulant covers the semiconductor elements and the first surface of the conductive structure. The encapsulant has a width ‘L’ and defines at least one notch portion. A minimum distance ‘d’ is between a bottom surface of the notch portion and the second surface of the conductive structure. The encapsulant has a Young's modulus ‘E’ and a rupture strength ‘Sr’, and L/(K×d)>E/Sr, wherein ‘K’ is a stress concentration factor with a value of greater than 1.2.