公开(公告)号：US06861316B2

公开(公告)日：2005-03-01

申请号：US10637212

申请日：2003-08-08

申请人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

发明人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  Y10S438/933

摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.

摘要翻译： 在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。 在基板上形成掩模，然后对基板进行图案化。 以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。 然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。 因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸镀部8。 此后，沟槽7a的壁被氧化。

公开(公告)号：US06917075B2

公开(公告)日：2005-07-12

申请号：US10752409

申请日：2004-01-07

申请人： Akira Inoue ,  Akira Asai ,  Teruhito Ohnishi ,  Haruyuki Sorada ,  Yoshihiro Hara ,  Takeshi Takagi

发明人： Akira Inoue ,  Akira Asai ,  Teruhito Ohnishi ,  Haruyuki Sorada ,  Yoshihiro Hara ,  Takeshi Takagi

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66772 ,  H01L21/76895 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78621

摘要： A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.

摘要翻译： 根据本发明的半导体器件及其制造方法是：在半导体衬底的预定区域上形成栅极绝缘体; 栅电极形成在栅极绝缘体上; 源极和漏极区域分别形成在预定区域的位于栅极电极的两侧的部分中; 由不同于所述源极和漏极区域的所述预定区域的区域形成的体区; 以及使所述栅电极和所述体区域电连接的触点，其中，与所述栅电极连接的所述触点的一部分在平面图中形成为与所述栅电极相交。

公开(公告)号：US06838395B1

公开(公告)日：2005-01-04

申请号：US10330080

申请日：2002-12-30

申请人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

发明人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

IPC分类号： C30B1/00 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/322 ,  H01L21/324

CPC分类号： H01L21/324 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/322 ,  Y10S438/933

摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

摘要翻译： 一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加 能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。 该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。

公开(公告)号：US06828602B2

公开(公告)日：2004-12-07

申请号：US10031445

申请日：2002-01-22

申请人： Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

发明人： Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

IPC分类号： H01L31072

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/7378 ,  Y10S438/936

摘要： A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

摘要翻译： 通过在Si衬底上的集电极层102上的外延生长，顺序地生长SiGe间隔层151，包括硼的梯度SiGe基极层152和Si覆盖层153。 在Si覆盖层153上形成第二沉积氧化物膜112，该第二沉积氧化物膜112具有基底开口部分118和将形成填充基部开口部分的发射极连接电极的P +多晶硅层115，形成发射极扩散层153a 通过将磷扩散到Si覆盖层153中。当Si覆盖层153生长时，通过原位掺杂使Si覆盖层153仅在其上部包含硼，则耗尽层的宽度 154变窄，并且复合电流降低，从而可以提高电流特性的线性。

公开(公告)号：US07049681B2

公开(公告)日：2006-05-23

申请号：US10972442

申请日：2004-10-26

申请人： Teruhito Ohnishi ,  Akira Asai

发明人： Teruhito Ohnishi ,  Akira Asai

IPC分类号： H01L29/02

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

摘要翻译： 作为由i-Si 1-x Ge x x构成的基底的Si 1-x Ge 2 x层111b， / SUB层，并且在集电极层102上形成有Si + 1-xSi Ge层，并且Si覆盖层111a 因为发射极形成在p + 1 Si 1-x Ge层上。 发射极引线电极129，其由含有等于或低于单晶硅的固溶度极限的磷的N +和/或多个多晶硅层129b组成， 在基底开口118中的Si覆盖层111a上形成含有高浓度的磷的多晶硅层129a。通过抑制Si覆盖层111a的基底层中的杂质浓度分布适当地保持 以过高浓度的磷（P）掺杂。 Si覆盖层111a的上部可以含有p型杂质。 因此，适当地维持NPN双极晶体管的基极层中的p型杂质浓度分布。

公开(公告)号：US06987072B2

公开(公告)日：2006-01-17

申请号：US11009020

申请日：2004-12-13

申请人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

发明人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

IPC分类号： H01L21/31

CPC分类号： H01L21/324 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/322 ,  Y10S438/933

摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

摘要翻译： 一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加 能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。 该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。

公开(公告)号：US06927118B2

公开(公告)日：2005-08-09

申请号：US10695478

申请日：2003-10-29

申请人： Ken Idota ,  Teruhito Ohnishi ,  Akira Asai

发明人： Ken Idota ,  Teruhito Ohnishi ,  Akira Asai

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

摘要： The present invention discloses a process of fabricating a semiconductor device comprising the steps of: forming a collector layer of a first conductivity type at a portion of a surface of a semiconductor substrate; forming a collector opening portion in a first insulating layer formed on the semiconductor substrate; epitaxially growing, on the semiconductor substrate of the collector opening portion, a semiconductor layer including a layer of a second conductivity type constituting a base layer; sequentially layering, on the semiconductor substrate, an etching stopper layer against dry etching and a masking layer against wet etching; exposing a part of the etching stopper layer by removing a part of the masking layer by means of dry etching; and by subjecting the exposed etching stopper layer to a wet etching treatment using the remaining masking layer as a mask, forming a base junction opening portion through the etching stopper layer and the masking layer.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括以下步骤：在半导体衬底的表面的一部分处形成第一导电类型的集电极层; 在形成在所述半导体衬底上的第一绝缘层中形成集电极开口部分; 在集电体开口部的半导体基板上外延生长构成基底层的具有第二导电类型的层的半导体层; 在半导体衬底上依次层叠抗干蚀刻的蚀刻停止层和抗蚀刻的掩模层; 通过干蚀刻去除一部分掩模层来暴露一部分蚀刻阻挡层; 并且通过使用剩余的掩模层作为掩模对暴露的蚀刻停止层进行湿法蚀刻处理，通过蚀刻停止层和掩​​模层形成基底连接开口部分。

公开(公告)号：US20050082571A1

公开(公告)日：2005-04-21

申请号：US10972442

申请日：2004-10-26

申请人： Teruhito Ohnishi ,  Akira Asai

发明人： Teruhito Ohnishi ,  Akira Asai

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737 ,  H01L29/739

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

摘要翻译： 作为由i-Si 1-x Ge x x构成的基底的Si 1-x Ge 2 x层111b， / SUB层，并且在集电极层102上形成有Si + 1-xSi Ge层，并且Si覆盖层111a 因为发射极形成在p + 1 Si 1-x Ge层上。 发射极引线电极129，其由含有等于或低于单晶硅的固溶度极限的磷的N +和/或多个多晶硅层129b组成， 在基底开口118中的Si覆盖层111a上形成含有高浓度的磷的多晶硅层129a。通过抑制Si覆盖层111a的基底层中的杂质浓度分布适当地保持 以过高浓度的磷（P）掺杂。 Si覆盖层111a的上部可以含有p型杂质。 因此，适当地维持NPN双极晶体管的基极层中的p型杂质浓度分布。

公开(公告)号：US06399993B1

公开(公告)日：2002-06-04

申请号：US09786551

申请日：2001-03-07

申请人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

发明人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

IPC分类号： H01L2972

CPC分类号： H01L21/76237 ,  H01L21/8249

摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.

摘要翻译： 在双极晶体管块中，SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）依次层叠在集电极扩散层（9）上。 在基底层（20a）的两个边缘上设置有由多晶硅制成的基底底涂层绝缘膜（5a）和基底延伸电极（22）。 基底层（20a）具有与基底底涂层绝缘膜（5a）的厚度相等的周边部分和比周边部分厚的中心部分。 用于CMOS块的基底涂层绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。 由于作为基底层的SiGe层与基底底涂层绝缘膜5a之间的热膨胀系数的差异导致的应力可以降低，并且实现了高可靠性的BiCMOS器件。

公开(公告)号：US07091099B2

公开(公告)日：2006-08-15

申请号：US10807307

申请日：2004-03-24

申请人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

发明人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

摘要翻译： 双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极 ，和发射极层。 在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。 发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。