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    Semiconductor sensor and method of manufacturing the same
    11.
    发明申请
    Semiconductor sensor and method of manufacturing the same 有权
    半导体传感器及其制造方法

    公开(公告)号：US20080202249A1

    公开(公告)日：2008-08-28

    申请号：US12010758

    申请日：2008-01-29

    申请人： Hisanori Yokura ,  Yoshihiko Isobe ,  Eishi Kawasaki

    发明人： Hisanori Yokura ,  Yoshihiko Isobe ,  Eishi Kawasaki

    IPC分类号： G01L9/04 ,  H01C17/28

    CPC分类号： G01L9/0055 ,  G01K5/52 ,  G01L1/2293 ,  H01L2224/02166 ,  Y10T29/49103

    摘要： A semiconductor pressure sensing apparatus includes a metallic stem having a diaphragm and a semiconductor sensor bonded to the diaphragm. The semiconductor sensor includes a gauge section and first and second bonding pads. The gauge section is configured to be deformed according to a deformation of the diaphragm. The first and second bonding pads are respectively connected to different positions of the gauge section so that an electrical resistance between the first and second bonding pads can change with a change in the deformation of the diaphragm. The gauge section is formed to a semiconductor layer of an silicon-on-insulator substrate. The semiconductor sensor is directly bonded to the diaphragm by activating contact surfaces between the semiconductor sensor and the diaphragm.

    摘要翻译： 一种半导体压力感测装置，包括具有隔膜的金属杆和结合到隔膜的半导体传感器。 半导体传感器包括测量部分和第一和第二接合焊盘。 仪表部分被配置为根据隔膜的变形而变形。 第一和第二接合焊盘分别连接到量规部分的不同位置，使得第一和第二接合焊盘之间的电阻随着隔膜变形的改变而改变。 测量部分形成为绝缘体上硅衬底的半导体层。 通过激活半导体传感器和隔膜之间的接触表面，半导体传感器直接接合到隔膜。

    Method of manufacturing semiconductor device
    12.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06908857B2

    公开(公告)日：2005-06-21

    申请号：US10657081

    申请日：2003-09-09

    申请人： Kazuo Akamatsu ,  Yoshihiko Isobe ,  Hiroyuki Yamane

    发明人： Kazuo Akamatsu ,  Yoshihiko Isobe ,  Hiroyuki Yamane

    IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/7685 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cm2 or less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path. This makes it possible to suppress or minimize unwanted fabrication of AlN on or above the surface of an Al containing lead pattern, thereby enabling increase in electromigration (EM) lifetime of electrical interconnect leads used.

    摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有硅衬底半导体元件和与其电连接的铝（Al）合金布线引线。 该方法包括以下步骤：在硅衬底上形成含有铜（Cu）的Al合金层，并且通过使用溅射技术在Al合金层上形成具有增强的化学反应性的氮化钛（TiN）膜，同时施加直流电力 为5.5W / cm 2以下。 在Al合金层上制备这种富含反应性的TiN膜导致Al和Ti的反应层被细分成几个间隔开的段。 在这种情况下，反应层几乎不作为任何扩散路径; 因此，可以防止Al合金层中所含的Cu作为其扩散路径而反向扩散。 这使得可以抑制或最小化在含铝的引线图案的表面上或上方的AlN的不希望的制造，从而能够增加使用的电互连引线的电迁移（EM）寿命。

    Physical sensor
    15.
    发明授权
    Physical sensor 失效
    物理传感器

    公开(公告)号：US08146426B2

    公开(公告)日：2012-04-03

    申请号：US12318186

    申请日：2008-12-23

    申请人： Kazuhiko Sugiura ,  Yoshihiko Isobe

    发明人： Kazuhiko Sugiura ,  Yoshihiko Isobe

    IPC分类号： G01P15/125 ,  G01P9/04 ,  G01C19/56

    CPC分类号： G01P15/125 ,  G01P15/0802 ,  G01P15/18 ,  G01P2015/082

    摘要： A physical sensor includes: a substrate having a silicon layer, an oxide film and a support layer; and a sensor portion having movable and fixed electrodes and a lower electrode. The movable electrode is supported by a beam on the support layer. The fixed electrode faces the movable electrode. The lower electrode is disposed on the support layer and faces the movable electrode. The physical sensor detects horizontal physical quantity based on a capacitance between the movable and fixed electrodes, and vertical physical quantity based on a capacitance between the movable and lower electrodes. The beam includes vertical and horizontal beams. The thickness of the vertical beam is smaller than the thickness of the horizontal beam.

    摘要翻译： 物理传感器包括：具有硅层，氧化膜和支撑层的衬底; 以及具有可移动和固定电极的传感器部分和下部电极。 可动电极由支撑层上的梁支撑。 固定电极面向可动电极。 下电极设置在支撑层上并面向可动电极。 物理传感器基于可移动和固定电极之间的电容以及基于可动电极和下电极之间的电容的垂直物理量来检测水平物理量。 梁包括垂直和水平梁。 垂直梁的厚度小于水平梁的厚度。

    Semiconductor device including several transistors and method of manufacturing the same
    16.
    发明授权
    Semiconductor device including several transistors and method of manufacturing the same 有权
    包括几个晶体管的半导体器件及其制造方法

    公开(公告)号：US06198140B1

    公开(公告)日：2001-03-06

    申请号：US09391449

    申请日：1999-09-08

    申请人： Hidetoshi Muramoto ,  Yoshihiko Isobe

    发明人： Hidetoshi Muramoto ,  Yoshihiko Isobe

    IPC分类号： H01L2976

    CPC分类号： H01L21/823456 ,  H01L21/823462

    摘要： In a semiconductor device including high-voltage, middle-voltage, and low voltage transistors having operating voltages different from one another, a gate length and a thickness of a gate oxide film are increased as the operating voltage is increased. Accordingly, in the high-voltage transistor, an electric field produced at a channel is relaxed. In the low-voltage transistor, a structure is made finer. A concentration of a well and an impurity amount implanted into a surface portion of a substrate are set to be identical with each other in all the transistors. Accordingly, the semiconductor device can be speedily manufactured at a high yield.

    摘要翻译： 在包括具有彼此不同的工作电压的高压，中压和低压晶体管的半导体器件中，栅极长度和栅极氧化膜的厚度随着工作电压的增加而增加。 因此，在高电压晶体管中，放宽了在通道产生的电场。 在低压晶体管中，结构更细。 注入到衬底的表面部分中的阱和杂质量的浓度在所有晶体管中彼此相同。 因此，可以高产率快速制造半导体器件。

    Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime
    19.
    发明授权
    Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime 有权
    半导体器件的电气布线能够增加电迁移（EM）寿命

    公开(公告)号：US06650017B1

    公开(公告)日：2003-11-18

    申请号：US09637066

    申请日：2000-08-11

    申请人： Kazuo Akamatsu ,  Yoshihiko Isobe ,  Hiroyuki Yamane

    发明人： Kazuo Akamatsu ,  Yoshihiko Isobe ,  Hiroyuki Yamane

    IPC分类号： H01L2348

    CPC分类号： H01L21/7685 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing a semiconductor device having on a silicon substrate semiconductor elements and aluminum (Al) alloy wiring leads as electrically connected thereto is disclosed. The method includes the steps of forming on the silicon substrate an Al alloy layer containing therein copper (Cu), and forming on the Al alloy layer a titanium nitride (TiN) film with enhanced chemical reactivity by using sputtering techniques while applying thereto a DC power of 5.5 W/cm2 or less. Fabrication of such reactivity-rich TiN film on the Al alloy layer results in a reaction layer of Al and Ti being subdivided into several spaced-apart segments. In this case, the reaction layer hardly serves as any diffusion path; thus, it becomes possible to prevent Cu as contained in the Al alloy layer from attempting to outdiffuse with the reaction layer being as its diffusion path. This makes it possible to suppress or minimize unwanted fabrication of AlN on or above the surface of an Al containing lead pattern, thereby enabling increase in electromigration (EM) lifetime of electrical interconnect leads used.

    摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有硅衬底半导体元件和与其电连接的铝（Al）合金布线引线。 该方法包括以下步骤：在硅衬底上形成含有铜（Cu）的Al合金层，并且通过使用溅射技术在Al合金层上形成具有增强的化学反应性的氮化钛（TiN）膜，同时施加直流电力 为5.5W / cm 2以下。 在Al合金层上制备这种富含反应性的TiN膜导致Al和Ti的反应层被细分成几个间隔开的段。 在这种情况下，反应层几乎不作为任何扩散路径; 因此，可以防止Al合金层中所含的Cu作为其扩散路径而反向扩散。 这使得可以抑制或最小化在含铝的引线图案的表面上或上方的AlN的不希望的制造，从而能够增加使用的电互连引线的电迁移（EM）寿命。

    Insulated gate transistor with leakage current prevention feature
    20.
    发明授权
    Insulated gate transistor with leakage current prevention feature 失效
    具有漏电流防护功能的绝缘栅晶体管

    公开(公告)号：US06337504B1

    公开(公告)日：2002-01-08

    申请号：US09031733

    申请日：1998-02-27

    申请人： Yoshihiko Isobe ,  Hidetoshi Muramoto ,  Hisayoshi Ooshima ,  Masahiro Ogino

    发明人： Yoshihiko Isobe ,  Hidetoshi Muramoto ,  Hisayoshi Ooshima ,  Masahiro Ogino

    IPC分类号： H01L2976

    CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  Y10S257/90

    摘要： An MIS transistor fabricated in a manner that minimizes the occurrence of leak currents and that improves overall transistor performance by minimizing variation in location of the transistor source and drain during fabrication thereof. A gate electrode is first fabricated on a substrate. Next, a thermal oxide layer is formed on a side of the gate electrode. A masking process is then performed with the thermal oxide layer to form a source and a drain. A silicon oxide layer is then deposited over the gate electrode, the source and the drain. An etching process is performed on the silicon oxide to form a side wall oxide film over the thermal oxide layer on the side of the gate electrode and to expose surfaces of the gate electrode, the source and the drain. A metal film is then deposited over the gate electrode, the source and the drain and is heat treated to form a metal silicide film on the exposed surfaces of the gate electrode, the source and the drain. The side wall oxide film functions to disperse the metal silicide film as it is deposited to electrically separate the gate electrode, the source and the drain, thereby preventing a leakage current from occurring.

    摘要翻译： 以最小化泄漏电流的发生的方式制造的MIS晶体管，并且通过使晶体管源极和漏极在其制造期间的位置的变化最小化来改善整体晶体管的性能。 首先在基板上制造栅电极。 接下来，在栅电极的一侧形成热氧化层。 然后用热氧化物层进行掩模处理以形成源极和漏极。 然后在栅电极，源极和漏极上沉积氧化硅层。 对氧化硅进行蚀刻处理，以在栅电极侧的热氧化层上形成侧壁氧化膜，并露出栅电极，源极和漏极的表面。 然后在栅电极，源极和漏极上沉积金属膜，并且在栅电极，源极和漏极的暴露表面上进行热处理以形成金属硅化物膜。 侧壁氧化膜用于在金属硅化物膜沉积时分散栅极电极，源极和漏极，从而防止发生漏电流。