公开(公告)号：US08347258B2

公开(公告)日：2013-01-01

申请号：US13028250

申请日：2011-02-16

Applicant: Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

Inventor： Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

IPC: G06F17/50

CPC classification number: G09G5/006 ,  G06F3/14 ,  Y02T10/82

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

Abstract translation: 包装包括模具和至少一个另外的模具。 管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。 管芯还具有映射电路，其被配置为向接收到的事务分配本地源身份信息作为源身份信息，本地源身份信息包括一组可重用的本地源身份信息。 这样可确保以相同原始来源身份和目标标记的事务的顺序，并允许以不同的源标识符标记的事务处理不正常。

公开(公告)号：US20110261603A1

公开(公告)日：2011-10-27

申请号：US12958646

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G11C5/06

CPC classification number: G06F13/4265 ,  G06F13/385 ,  H01L2224/16225 ,  H01L2924/15311 ,  Y02D10/14 ,  Y02D10/151

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals is greater than a width of the interface. At least one of the first and second dies performs a configurable grouping so as to provide a plurality of groups of control signals. The signals within a group are transmitted across the interface together.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口被配置为传送多个控制信号。 控制信号的数量大于接口的宽度。 第一和第二模具中的至少一个模具执行可配置分组，以便提供多组控制信号。 组内的信号一起通过接口传输。

公开(公告)号：US20110138093A1

公开(公告)日：2011-06-09

申请号：US12960713

申请日：2010-12-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F13/24 ,  G06F12/00

CPC classification number: G06F13/24 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 该包装包括用于检测中断信息的中断处理和响应于中断信息检测提供分组。 分组包括要写入分组中的数据的地址。 该接口被配置为在信元之间传送数据包。 提供数据可写入的数据存储。 从几个数据包中接收的数据确定中断事件。

公开(公告)号：US20110133825A1

公开(公告)日：2011-06-09

申请号：US12958639

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: H01L25/00

CPC classification number: G06F13/385 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 采样电路在接口传输之前对控制信号进行采样。 取决于与相应控制信号相关联的至少一个服务质量参数来控制采样电路。

公开(公告)号：US09311246B2

公开(公告)日：2016-04-12

申请号：US12284331

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit capable of retrieving the portion of data from the system memory. The systems and methods further comprise a status memory for identifying whether or not a region of the cache memory contains data that has been accessed from the cache memory by an external device.

公开(公告)号：US09026774B2

公开(公告)日：2015-05-05

申请号：US13560294

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F9/00 ,  G06F9/44 ,  G06F12/06

CPC classification number: G06F9/4403 ,  G06F12/0638

Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.

Abstract translation: 一种第一装置，包括配置成从具有第一存储器空间的第二装置接收具有地址的事务的接口; 翻译器，被配置为将第一类型的接收到的事务的地址转换到第一布置的第二存储器空间，第二存储器空间不同于第一存储器空间; 以及引导逻辑，被配置为将所接收的事务的引导事务映射到所述第二存储器空间中的引导区域。

公开(公告)号：US08990540B2

公开(公告)日：2015-03-24

申请号：US13560414

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/10 ,  G06F13/16

CPC classification number: G06F13/1657 ,  G06F13/14 ,  G06F13/385

Abstract: A method may include receiving, at a first integrated circuit die, a memory transaction having an address from a second integrated circuit die. The method may further include determining, at the first integrated circuit die and based on the address, if the transaction is for the first integrated circuit die and, if so, translating the address. If transaction is for a third integrated circuit die, the transaction may be transmitted, without modification to the address, to the third integrated circuit die. The translation may be based upon a first table with each entry including a first address and a second translated address corresponding to the first address, and a second table with each entry including a first address and an indication if the transaction is to be forwarded without modification to the address.

Abstract translation: 一种方法可以包括在第一集成电路管芯处接收具有来自第二集成电路管芯的地址的存储器事务。 该方法还可以包括在第一集成电路管芯处并基于地址确定该事务是否用于第一集成电路管芯，如果是，则转换该地址。 如果交易是用于第三集成电路管芯，则可以向第三集成电路管芯传送事务，而不改变地址。 翻译可以基于第一表，其中每个条目包括对应于第一地址的第一地址和第二翻译地址，以及第二表，其中每个条目包括第一地址和指示，如果交易将被转发而不进行修改 到地址。

公开(公告)号：US08930637B2

公开(公告)日：2015-01-06

申请号：US13489920

申请日：2012-06-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G06F12/0891 ,  G06F12/0815 ,  G06F12/0817 ,  G06F13/1663

Abstract: An arrangement includes a first part and a second part. The first part includes a memory controller for accessing a memory, at least one first cache memory and a first directory. The second part includes at least one second cache memory configured to request access to said memory. The first directory is configured to use a first coherency protocol for the at least one first cache memory and a second different coherency protocol for the at least one second memory.

Abstract translation: 一种装置包括第一部分和第二部分。 第一部分包括用于访问存储器，至少一个第一高速缓冲存储器和第一目录的存储器控​​制器。 第二部分包括被配置为请求访问所述存储器的至少一个第二高速缓存存储器。 第一目录被配置为对于至少一个第一高速缓存存储器使用第一一致性协议，以及对于至少一个第二存储器使用第二不同一致性协议。

公开(公告)号：US08629544B2

公开(公告)日：2014-01-14

申请号：US12958622

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: H01L23/02 ,  H01L29/40

CPC classification number: G11C7/10 ,  G06F13/16 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04N21/426 ,  Y02D10/14

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 提供多路复用器以将控制信号和存储器事务复用到接口上，使得所述接口的多个连接由控制信号和存储器事务共享。

公开(公告)号：US20130031312A1

公开(公告)日：2013-01-31

申请号：US13560491

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0802 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: A cache memory controller including: a pre-fetch requester configured to issue pre-fetch requests, each pre-fetch request having one of a plurality of different quality of services.

Abstract translation: 一种高速缓冲存储器控制器，包括：预取请求器，被配置为发出预取请求，每个预取请求具有多个不同服务质量中的一个。