公开(公告)号：US09058283B2

公开(公告)日：2015-06-16

申请号：US13560559

申请日：2012-07-27

Applicant: Stuart Ryan ,  Andrew Michael Jones

Inventor： Stuart Ryan ,  Andrew Michael Jones

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract translation: 一种第一高速缓存装置，包括被配置为从第二高速缓存装置接收存储器请求的输入; 用于存储数据的第一高速缓冲存储器; 输出，被配置为提供对所述第二高速缓存装置的所述存储器请求的响应; 和第一缓存控制器; 第一缓存控制器被配置为使得对于由输出输出的存储器请求的响应，高速缓存存储器不包括与存储器请求相关联的数据的分配。

公开(公告)号：US08347258B2

公开(公告)日：2013-01-01

申请号：US13028250

申请日：2011-02-16

Applicant: Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

Inventor： Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

IPC: G06F17/50

CPC classification number: G09G5/006 ,  G06F3/14 ,  Y02T10/82

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

Abstract translation: 包装包括模具和至少一个另外的模具。 管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。 管芯还具有映射电路，其被配置为向接收到的事务分配本地源身份信息作为源身份信息，本地源身份信息包括一组可重用的本地源身份信息。 这样可确保以相同原始来源身份和目标标记的事务的顺序，并允许以不同的源标识符标记的事务处理不正常。

公开(公告)号：US20110261603A1

公开(公告)日：2011-10-27

申请号：US12958646

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G11C5/06

CPC classification number: G06F13/4265 ,  G06F13/385 ,  H01L2224/16225 ,  H01L2924/15311 ,  Y02D10/14 ,  Y02D10/151

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals is greater than a width of the interface. At least one of the first and second dies performs a configurable grouping so as to provide a plurality of groups of control signals. The signals within a group are transmitted across the interface together.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口被配置为传送多个控制信号。 控制信号的数量大于接口的宽度。 第一和第二模具中的至少一个模具执行可配置分组，以便提供多组控制信号。 组内的信号一起通过接口传输。

公开(公告)号：US20110138093A1

公开(公告)日：2011-06-09

申请号：US12960713

申请日：2010-12-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F13/24 ,  G06F12/00

CPC classification number: G06F13/24 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 该包装包括用于检测中断信息的中断处理和响应于中断信息检测提供分组。 分组包括要写入分组中的数据的地址。 该接口被配置为在信元之间传送数据包。 提供数据可写入的数据存储。 从几个数据包中接收的数据确定中断事件。

公开(公告)号：US20110133825A1

公开(公告)日：2011-06-09

申请号：US12958639

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: H01L25/00

CPC classification number: G06F13/385 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 采样电路在接口传输之前对控制信号进行采样。 取决于与相应控制信号相关联的至少一个服务质量参数来控制采样电路。

公开(公告)号：US06658514B1

公开(公告)日：2003-12-02

申请号：US09301651

申请日：1999-04-28

Applicant: Andrew Michael Jones ,  Michael David May

Inventor： Andrew Michael Jones ,  Michael David May

IPC: G06F1340

CPC classification number: G06F13/385

Abstract: A computer system comprises on-chip a CPU with at least one different module, both having circuitry to generate two types of address request packets, one being a control command packet to which a destination device must respond on receipt and the other type being an interrupt request with a priority indicator for a selective response by the destination device.

Abstract translation: 计算机系统包括具有至少一个不同模块的CPU的片上，两者具有生成两种类型的地址请求分组的电路，一个是目的地设备在接收时必须响应的控制命令分组，另一种类型是中断 请求具有目标设备的选择性响应的优先级指示符。

公开(公告)号：US06356960B1

公开(公告)日：2002-03-12

申请号：US09710775

申请日：2000-11-09

Applicant: Andrew Michael Jones ,  David Alan Edwards ,  Michael David May

Inventor： Andrew Michael Jones ,  David Alan Edwards ,  Michael David May

IPC: G06F1314

CPC classification number: G06F11/3656

Abstract: There is disclosed a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a debugging port connected to a communication bus on the integrated circuit and to an external debugging computer device. The external debugging device is operable to transmit control signals through the debugging port: a) to stop execution by the CPU of instructions obtained from a first on-chip memory; b) to provide from a second memory associated with the external debugging computer device a debugging routine to be executed by the CPU; and c) to restart operation of the CPU after the routine with execution of instructions from an address determined by the external debugging device. The on-chip CPU is operable with code in the first memory which is independent of the debugging routine. A method of operating such a computer system with an external debugging device is also disclosed.

Abstract translation: 公开了一种包括在集成电路芯片上的微处理器的计算机系统，该集成电路芯片包括片上CPU和连接到集成电路上的通信总线的调试端口以及外部调试计算机设备。 外部调试装置可操作以通过调试端口发送控制信号：a）停止CPU执行从第一片上存储器获得的指令; b）从与外部调试计算机设备相关联的第二存储器提供要由CPU执行的调试例程; 以及c）在从由外部调试装置确定的地址执行指令的例程之后重新启动CPU的操作。 片上CPU可操作于独立于调试例程的第一存储器中的代码。 还公开了一种使用外部调试装置操作这种计算机系统的方法。

公开(公告)号：US06351790B1

公开(公告)日：2002-02-26

申请号：US09270142

申请日：1999-03-16

Applicant: Andrew Michael Jones

Inventor： Andrew Michael Jones

IPC: G06F1214

CPC classification number: G06F12/0837 ,  G06F12/0815

Abstract: A cache coherency mechanism for a computer system having a plurality of processors, each for executing a sequence of instructions, at least one of the processors having a cache memory associated therewith. The computer system includes a memory that provides an address space where data items are stored for use by all of the processors. A behavior store holds in association with an address of each item, a cache behavior identifying the cacheable behavior of the item, the cacheable behaviors including a software coherent behavior and an automatically coherent behavior. When a cache coherency operation is instigated by a cache coherency instruction, the operation is effected dependent on the cacheable behavior associated with the specified address of the item. Methods for modifying the coherency status of a cache are also described.

Abstract translation: 一种用于具有多个处理器的计算机系统的高速缓存一致性机制，每个处理器用于执行指令序列，所述处理器中的至少一个具有与其相关联的高速缓冲存储器。 计算机系统包括提供数据项目被存储以供所有处理器使用的地址空间的存储器。 行为存储与每个项目的地址，识别项目的可缓存行为的缓存行为，包括软件相关行为的可缓存行为和自动相关行为相关联。 当缓存一致性操作由高速缓存一致性指令引发时，该操作取决于与项目的指定地址相关联的可缓存行为。 还描述了用于修改高速缓存的相关性状态的方法。

公开(公告)号：US5828852A

公开(公告)日：1998-10-27

申请号：US562802

申请日：1995-11-27

Applicant: Thomas Niedermeier ,  Peter Rohm ,  Richard Schmid ,  David Flynn ,  Peter Klapproth ,  Frederik Zandveld ,  Jacobus Christophorus Koot ,  Andrew Michael Jones ,  James Graham Matthew ,  Bruno Douady

Inventor： Thomas Niedermeier ,  Peter Rohm ,  Richard Schmid ,  David Flynn ,  Peter Klapproth ,  Frederik Zandveld ,  Jacobus Christophorus Koot ,  Andrew Michael Jones ,  James Graham Matthew ,  Bruno Douady

IPC: G06F13/364 ,  G06F13/00

CPC classification number: G06F13/364

Abstract: A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.

Abstract translation: 一种用于总线系统操作的方法和电路配置。 总线包括总线控制单元，其仅控制仲裁，并且在数据传输期间超过时间。 在相应的主动主单元和寻址的从单元中确定实际的数据传输。 诸如数据长度，对数据区域或控制区域的访问和等待周期的总线周期的特性通过多个控制线以编码形式被传送。

公开(公告)号：US09086870B2

公开(公告)日：2015-07-21

申请号：US13560237

申请日：2012-07-27

Applicant: Stuart Ryan ,  Andrew Michael Jones

Inventor： Stuart Ryan ,  Andrew Michael Jones

IPC: H04L12/28 ,  G06F1/30 ,  H04W52/02

CPC classification number: G06F1/30 ,  H04W52/0277 ,  Y02D70/142 ,  Y02D70/23

Abstract: A circuit including an initiator of a transaction, an interconnect, and a controller. The controller is configured in response to a condition in a least one first part of the circuit to send a notification via the interconnect to at least one block in a second part of the circuit. The notification includes information about the condition in the first part of the circuit, the condition preventing a response to the transaction from being received by the initiator.

Abstract translation: 包括交易的发起者，互连和控制器的电路。 控制器被配置为响应于电路的至少一个第一部分中的状态，以经由互连发送通知给电路的第二部分中的至少一个块。 该通知包括关于电路的第一部分中的状况的信息，防止由发起者接收到对事务的响应的条件。