公开(公告)号：US10963172B2

公开(公告)日：2021-03-30

申请号：US16059766

申请日：2018-08-09

Applicant: Apple Inc.

Inventor： Nachiappan Chidambaram Nachiappan ,  David L. Trawick ,  Yiu Chun Tse ,  Deniz Balkan ,  Hengsheng Geng ,  Shawn Munetoshi Fukami ,  Jaideep Dastidar ,  Benjamin K. Dodge ,  Vinodh R. Cuppu

IPC: G06F3/06 ,  G06F13/16 ,  H04W72/04 ,  H04W28/02 ,  H04L12/853

Abstract: A system and method for efficiently allocating data storage to agents. A computing system includes an interconnect with intermediate buffers for storing transactions and corresponding payload data during transport between sources and destinations. A data storage limit is set on an amount of data storage corresponding to outstanding transactions for each of the multiple sources based on the initial buffer assignments. A number of outstanding transactions for each of the multiple sources is limited based on a corresponding data storage limit. If the rate of allocation of a given buffer assigned to a first source exceeds a threshold, then a second source is selected with available space exceeding a threshold in an assigned buffer. If it is determined the second source is not assigned to a buffer with a rate of allocation exceeding a threshold, then buffer storage is reassigned from the second source to the first source.

公开(公告)号：US09495318B2

公开(公告)日：2016-11-15

申请号：US14089237

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Jim J. Lin ,  Timothy R. Paaske ,  Ben D. Jarrett

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/362 ,  G06F13/364

CPC classification number: G06F13/405 ,  G06F13/362 ,  G06F13/364 ,  G06F13/4027

Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

Abstract translation: 公开了桥单元和系统的实施例，其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令，这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令，并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分，则所有桥单元可以执行fence命令 。

公开(公告)号：US09053058B2

公开(公告)日：2015-06-09

申请号：US13721665

申请日：2012-12-20

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Deniz Balkan ,  Kevin C. Wong

IPC: H04L12/54 ,  G06F13/14

CPC classification number: G06F13/14 ,  G06F13/1642 ,  G06F13/1673

Abstract: Systems and methods for upgrading QoS levels of older transactions based on the presence of higher level QoS transactions in a given queue. A counter may be maintained to track the number of transactions in a queue that are assigned a corresponding QoS level. Each separate QoS level can have a corresponding counter. When a transaction is received by the queue, the counter corresponding to the QoS level of the transaction is incremented. When a transaction leaves the queue, the transaction is upgraded to the highest QoS level with a non-zero counter. Also, when the transaction leaves the queue, the counter corresponding to the original QoS level of the transaction is decremented.

Abstract translation: 基于在给定队列中存在较高级别的QoS事务，升级旧事务的QoS级别的系统和方法。 可以维护计数器来跟踪被分配相应QoS级别的队列中的事务的数量。 每个单独的QoS级别可以有一个相应的计数器。 当队列接收到事务时，增加对应于事务的QoS级别的计数器。 当事务离开队列时，事务将使用非零计数器升级到最高的QoS级别。 此外，当事务离开队列时，对应于事务的原始QoS级别的计数器递减。

公开(公告)号：US20140372699A1

公开(公告)日：2014-12-18

申请号：US13915911

申请日：2013-06-12

Applicant: Apple Inc.

Inventor： Shailendra S. Desai ,  Gurjeet S. Saund ,  Deniz Balkan ,  James Wang

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0802 ,  G06F12/0888 ,  G06F12/12 ,  Y02D10/13

Abstract: Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a transaction, and the first cache hint is compliant with a first protocol. The first cache hint can be set to a reserved encoding value as defined by the first protocol. Prior to the transaction being sent to the memory subsystem, the first cache hint is translated into a second cache hint. The memory subsystem recognizes cache hints which are compliant with a second protocol, and the second cache hint is compliant with the second protocol.

Abstract translation: 用于翻译SoC中不同协议之间的缓存提示的系统和方法。 SoC中的请求代理生成用于事务的第一高速缓存提示，并且第一高速缓存提示符合第一协议。 第一个缓存提示可以设置为第一个协议定义的保留编码值。 在将事务发送到存储器子系统之前，第一高速缓存提示被转换成第二高速缓存提示。 存储器子系统识别符合第二协议的高速缓存提示，并且第二高速缓存提示符合第二协议。

公开(公告)号：US20140181824A1

公开(公告)日：2014-06-26

申请号：US13721665

申请日：2012-12-20

Applicant: APPLE INC.

Inventor： Gurjeet S. Saund ,  Deniz Balkan ,  Kevin C. Wong

IPC: G06F9/54

CPC classification number: G06F13/14 ,  G06F13/1642 ,  G06F13/1673

Abstract: Systems and methods for upgrading QoS levels of older transactions based on the presence of higher level QoS transactions in a given queue. A counter may be maintained to track the number of transactions in a queue that are assigned a corresponding QoS level. Each separate QoS level can have a corresponding counter. When a transaction is received by the queue, the counter corresponding to the QoS level of the transaction is incremented. When a transaction leaves the queue, the transaction is upgraded to the highest QoS level with a non-zero counter. Also, when the transaction leaves the queue, the counter corresponding to the original QoS level of the transaction is decremented.

Abstract translation: 基于在给定队列中存在较高级别的QoS事务，升级旧事务的QoS级别的系统和方法。 可以维护计数器来跟踪被分配相应QoS级别的队列中的事务的数量。 每个单独的QoS级别可以有一个相应的计数器。 当队列接收到事务时，增加对应于事务的QoS级别的计数器。 当事务离开队列时，事务将使用非零计数器升级到最高的QoS级别。 此外，当事务离开队列时，对应于事务的原始QoS级别的计数器递减。

公开(公告)号：US20210303486A1

公开(公告)日：2021-09-30

申请号：US17242051

申请日：2021-04-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Christopher D. Shuler ,  Srinivasa Rangan Sridharan ,  Yu Zhang ,  Kaushik Kannan ,  Deniz Balkan

IPC: G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

公开(公告)号：US10255218B1

公开(公告)日：2019-04-09

申请号：US16017198

申请日：2018-06-25

Applicant: Apple Inc.

Inventor： Yiu Chun Tse ,  Deniz Balkan ,  Vinodh R. Cuppu ,  Shawn Munetoshi Fukami ,  Jaideep Dastidar ,  Hengsheng Geng

IPC: G06F13/40 ,  G06F13/20

Abstract: A system and method for efficiently bridging two communication protocols. In various embodiments, a computing system includes an interconnect for routing traffic among agents and endpoints. The agents use a first communication protocol and the endpoints use a second communication protocol that differs from the first protocol with regard to at least the ordering that is enforced between transactions. A bridge selects transactions of a first type and a second type used in the first protocol for processing based on the first protocol ordering while using acknowledgments used by the second protocol.

公开(公告)号：US09647653B2

公开(公告)日：2017-05-09

申请号：US14730473

申请日：2015-06-04

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Jean-Didier Allegrucci ,  Timothy Paaske ,  Deniz Balkan

IPC: H03K5/19 ,  H03K5/26

CPC classification number: H03K5/19 ,  H03K5/26

Abstract: An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.

公开(公告)号：US09152588B2

公开(公告)日：2015-10-06

申请号：US13653151

申请日：2012-10-16

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Erik P Machnicki ,  Deniz Balkan

IPC: G06F13/24 ,  G06F13/26

CPC classification number: G06F13/24 ,  G06F13/26 ,  Y02D10/14

Abstract: In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.

Abstract translation: 在一个实施例中，系统包括耦合到外围设备的至少一个外围设备，中断控制器，存储器控制器，至少一个CPU以及中断消息电路。 中断消息电路可以被耦合以从外围设备接收中断信号，并且可以被配置为生成用于在通信结构上传输的中断消息。 在一些实施例中，可以存在多个外围设备，其具有通过该结构的独立路径，用于存储器操作到存储器控制器。 每个这样的外设可以耦合到中断消息电路的一个实例。 在一个实施例中，中断是电平敏感的。 中断消息电路可以被配置为向中断控制器发送中断设置消息中断清除消息以指示电平。

公开(公告)号：US20140317323A1

公开(公告)日：2014-10-23

申请号：US13868313

申请日：2013-04-23

Applicant: APPLE INC.

Inventor： Benjamin K. Dodge ,  Deniz Balkan ,  Gurjeet S. Saund ,  Munetoshi Fukami

IPC: G06F13/368

CPC classification number: G06F13/368 ,  G06F13/16

Abstract: A method and apparatus for arbitration. In one embodiment, a point in a network includes first and second arbiters. Arbitration of transactions associated with an address within a first range are conducted in the first arbiter, while arbitration of transactions associated with an address within a second range are conducted in the second arbiter. Each transaction is one of a number of different transaction types having a respective priority level. A measurement circuit is coupled to receive information from the first and second arbiters each cycle indicating the type of transactions that won their respective arbitrations. The measurement circuit may update a number of credits associated with the types of winning transactions. The updated number of credits may be provided to both the first and second arbiters, and may be used as a basis for arbitration in the next cycle.

Abstract translation: 一种用于仲裁的方法和装置。 在一个实施例中，网络中的一个点包括第一和第二仲裁器。 与第一范围内的地址相关联的交易的仲裁在第一仲裁器中进行，而与第二范围内的地址相关联的交易的仲裁在第二仲裁器中进行。 每个事务是具有相应优先级的多个不同事务类型之一。 耦合测量电路以从第一和第二仲裁器接收信息，每个周期指示赢得其各自仲裁的交易的类型。 测量电路可以更新与获胜交易的类型相关联的多个信用。 可以将更新的信用数量提供给第一和第二仲裁器，并且可以用作下一周期中的仲裁的基础。