公开(公告)号：US20180232043A1

公开(公告)日：2018-08-16

申请号：US15430686

申请日：2017-02-13

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Inder M. Sodhi ,  Gerard R. Williams, III

IPC: G06F1/32

CPC classification number: G06F1/263 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

公开(公告)号：US09829948B2

公开(公告)日：2017-11-28

申请号：US14858035

申请日：2015-09-18

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Jafar Savoj ,  Inder M. Sodhi ,  Cyril de la Cropte de Chanterac ,  Sotirios Zogopoulos

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/28 ,  G01R19/255 ,  G01R19/25 ,  G06F1/26

CPC classification number: G06F1/28 ,  G01R19/2506 ,  G01R19/255 ,  G06F1/26 ,  G06F1/263

Abstract: An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.

公开(公告)号：US09503068B1

公开(公告)日：2016-11-22

申请号：US15068003

申请日：2016-03-11

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Sanjay Pant ,  Sotirios Zogopoulos ,  Jafar Savoj ,  Inder M. Sodhi

IPC: H03D1/00 ,  H03K5/00 ,  H03K5/159 ,  H03L7/06 ,  G01R19/04

CPC classification number: H03K5/159 ,  G01R19/04

Abstract: In an embodiment, a supply voltage envelope detector circuit is configured to detect a shape of the supply voltage over time and to compare the detected shape to expected shapes that indicate voltage droop events for which corrective action may be needed. The expected shapes may be predetermined based on one or more of: the design of the integrated circuit that includes the supply voltage envelope detector circuit; attributes of the power management unit (PMU) that is to generate the supply voltage for the integrated circuit; and/or attributes of the system that includes the integrated circuit. The shape of the voltage droop may experience little variation during use, and thus may be used to detect a droop event earlier and more accurately than a threshold-based mechanism, in some embodiments.

Abstract translation: 在一个实施例中，电源电压包络检测器电路被配置为随时间检测电源电压的形状，并将检测到的形状与指示可能需要校正动作的电压下降事件的预期形状进行比较。 预期形状可以基于以下中的一个或多个来预先确定：包括电源电压包络检测器电路的集成电路的设计; 用于生成集成电路的电源电压的电源管理单元（PMU）的属性; 和/或包括集成电路的系统的属性。 在一些实施例中，电压下降的形状可能在使用期间几乎没有变化，因此可以用于比基于阈值的机制更早和更准确地检测下垂事件。

公开(公告)号：US20250157730A1

公开(公告)日：2025-05-15

申请号：US19028277

申请日：2025-01-17

Applicant: Apple Inc.

Inventor： David P. Cappabianca ,  Joseph T. DiBene, II ,  Shawn Searles ,  Le Wang ,  Yizhang Yang ,  Sean Cian O'Mathuna ,  Santosh Kulkarni ,  Paul McCloskey ,  Zoran Pavlovic ,  William Lawton ,  Graeme Maxwell ,  Joseph O'Brien ,  Hugh Charles Smiddy

IPC: H01F41/34 ,  H01F17/00 ,  H01F19/00 ,  H01F27/28 ,  H10D1/20

Abstract: An inductor is disclosed, including a first wire, a non-conductive material, and a shell. The non-conductive material may cover the first wire, with a portion of each end of the first wire uncovered. The shell may include a top portion and a bottom portion and include at least one magnetized layer and at least one gap between the first portion and the second portion. The shell may also surround a portion of the non-conductive material.

公开(公告)号：US20240243012A1

公开(公告)日：2024-07-18

申请号：US18622588

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems including voltage regulator circuits are disclosed. In one embodiment, an apparatus includes a voltage regulator controller integrated circuit (IC) die including one or more portions of a voltage regulator circuit. The apparatus further includes a capacitor die, an inductor die, and an interconnect layer arranged over the voltage regulator controller IC die, the capacitor die and the inductor die. The interconnect provides electrical connections between the voltage regulator controller IC die, the capacitor die and the inductor die to form the voltage regulator circuit. In a further embodiment, the voltage regulator controller IC die, the capacitor die and the inductor die are arranged in a planar fashion within a voltage regulator module. In still another embodiment, a system IC is coupled to the voltage regulator module and includes one or more functional circuit blocks coupled to receive a regulated supply voltage generated by the voltage regulator circuit.

公开(公告)号：US20230335440A1

公开(公告)日：2023-10-19

申请号：US18307554

申请日：2023-04-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/17 ,  H01L2924/1427 ,  H01L2924/1436 ,  H01L2924/19042 ,  H01L2924/1432 ,  H01L2924/19103 ,  H01L2224/12105 ,  H01L2224/1703 ,  H01L2924/19104 ,  H01L2224/16265 ,  H01L2924/15192 ,  H01L2224/16235 ,  H01L2924/19041 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2924/1433 ,  H01L2924/18162 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/17181 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US11670548B2

公开(公告)日：2023-06-06

申请号：US17080609

申请日：2020-10-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US20220137692A1

公开(公告)日：2022-05-05

申请号：US17528380

申请日：2021-11-17

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Inder M. Sodhi ,  Keith Cox ,  Gerard R. Williams, III

IPC: G06F1/3206 ,  G06F1/3203 ,  G06F1/3296

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

公开(公告)号：US11204636B2

公开(公告)日：2021-12-21

申请号：US16519347

申请日：2019-07-23

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Inder M. Sodhi ,  Keith Cox ,  Gerard R. Williams, III

IPC: G06F1/3206 ,  G06F1/3203 ,  G06F1/3296

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

公开(公告)号：US10423209B2

公开(公告)日：2019-09-24

申请号：US15430699

申请日：2017-02-13

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Inder M. Sodhi ,  Keith Cox ,  Gerard R. Williams, III

IPC: G06F9/00 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/3203

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.