公开(公告)号：US20170323883A1

公开(公告)日：2017-11-09

申请号：US15658670

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/06 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L21/77 ,  H01L49/02

CPC classification number: H01L27/0641 ,  H01L21/77 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

公开(公告)号：US20160300813A1

公开(公告)日：2016-10-13

申请号：US14680539

申请日：2015-04-07

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Chonghua Zhong ,  Mengzhi Pang ,  Se Young Yang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83

Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，包装包括直接形成在顶模上的再分配层（RDL）和安装在RDL的后表面上的底模。

公开(公告)号：US20150303149A1

公开(公告)日：2015-10-22

申请号：US14331363

申请日：2014-07-15

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Mengzhi Pang ,  Se Young Yang ,  Leland W. Lew

IPC: H01L23/552 ,  H01L23/367 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2224/81

Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.

Abstract translation: 在一些实施例中，半导体器件封装组件可以包括第一衬底。 第一衬底可以包括电连接组件的第一组电导体。 在一些实施例中，组件可以包括耦合到第一衬底的至少一个电导体，使得电导体中的至少一个暴露于半导体器件封装组件的周边表面。 在一些实施例中，组件可以包括使用第二组电导体电连接到第一衬底的第二表面的第一裸片。 组件可以包括耦合到第一管芯的电子存储器模块。 在一些实施例中，组件可以包括施加到组件的上表面并且电耦合到暴露的电导体中的至少一个的屏蔽。 在使用过程中，屏蔽可能会阻碍电磁干扰。

公开(公告)号：US10818632B1

公开(公告)日：2020-10-27

申请号：US15943673

申请日：2018-04-02

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/77

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US10103138B2

公开(公告)日：2018-10-16

申请号：US15658670

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/08 ,  H01L27/06 ,  H01L21/77 ,  H01L49/02 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

公开(公告)号：US20170018546A1

公开(公告)日：2017-01-19

申请号：US15057588

申请日：2016-03-01

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/77

CPC classification number: H01L27/0641 ,  H01L21/77 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

Abstract translation: 在一些实施例中，系统可以包括集成电路。 集成电路可以包括包括第一表面，基本上与第一表面相对的第二表面的衬底和耦合到第一表面的第一组电导体。 第一组电导体可以用于将集成电路电连接到电路板。 集成电路可以包括使用第二组电导体耦合到衬底的第二表面的半导体管芯。 集成电路可以包括被定义为与集成电路集成的无源器件。 无源器件可以位于第二表面和第一组电导体中的至少一个之间。 芯片可以电连接到无源器件的第二侧。 无源器件的第一侧可用于电连接到第二器件。

公开(公告)号：US20160260684A1

公开(公告)日：2016-09-08

申请号：US14638925

申请日：2015-03-04

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Kwan-Yu Lai ,  Mengzhi Pang ,  Chonghua Zhong ,  Se Young Yang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL）以及附接到第一RDL的前侧和后侧的多个管芯。 第一和第二RDL与从第一RDL的后侧延伸到第二RDL的前侧的多个导电柱连接在一起。

公开(公告)号：US20200176427A1

公开(公告)日：2020-06-04

申请号：US16205679

申请日：2018-11-30

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chonghua Zhong ,  Jun Zhai ,  Long Huang ,  Mengzhi Pang ,  Rohan U. Mandrekar

IPC: H01L25/16 ,  H01L21/66 ,  G01R31/02

Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.

公开(公告)号：US09659907B2

公开(公告)日：2017-05-23

申请号：US14680539

申请日：2015-04-07

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Chonghua Zhong ,  Mengzhi Pang ,  Se Young Yang

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83

Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.

公开(公告)号：US20240243012A1

公开(公告)日：2024-07-18

申请号：US18622588

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems including voltage regulator circuits are disclosed. In one embodiment, an apparatus includes a voltage regulator controller integrated circuit (IC) die including one or more portions of a voltage regulator circuit. The apparatus further includes a capacitor die, an inductor die, and an interconnect layer arranged over the voltage regulator controller IC die, the capacitor die and the inductor die. The interconnect provides electrical connections between the voltage regulator controller IC die, the capacitor die and the inductor die to form the voltage regulator circuit. In a further embodiment, the voltage regulator controller IC die, the capacitor die and the inductor die are arranged in a planar fashion within a voltage regulator module. In still another embodiment, a system IC is coupled to the voltage regulator module and includes one or more functional circuit blocks coupled to receive a regulated supply voltage generated by the voltage regulator circuit.