公开(公告)号：US20220357670A1

公开(公告)日：2022-11-10

申请号：US17740750

申请日：2022-05-10

Applicant: Applied Materials, Inc.

Inventor： Joseph R. Johnson ,  Christopher Dennis Bencher

IPC: G03F7/20

Abstract: Methods for patterning a substrate are described. A substrate is scanned using a spatial light modulator with a plurality of exposures timed according to a non-crystalline shot pattern. Lithography systems for performing the substrate patterning method and non-transitory computer-readable medium for executing the patterning method are also described.

公开(公告)号：US10684555B2

公开(公告)日：2020-06-16

申请号：US15933147

申请日：2018-03-22

Applicant: Applied Materials, Inc.

Inventor： Joseph R. Johnson ,  Christopher Dennis Bencher

IPC: G03F7/20 ,  G03F7/00 ,  H01S5/30 ,  H01L27/15 ,  H01L33/32 ,  H01S5/40 ,  H01S5/026

Abstract: Embodiments of the present disclosure generally relate to an image projection system. The image projection system includes an active matrix solid state emitter (SSE) device. The active matrix solid state emitter includes a substrate, a silicon layer, and a emitter substrate. The silicon layer is deposited over the substrate having a plurality of transistors formed therein. The emitter substrate is positioned between the silicon layer and the substrate. The emitter substrate comprises a plurality of emitter arrays. Each emitter array defines a pixel, wherein one pixel comprises one or more transistors from the plurality of transistors. Each transistor is configured to receive a variable amount of current.

公开(公告)号：US10591815B2

公开(公告)日：2020-03-17

申请号：US16021350

申请日：2018-06-28

Applicant: Applied Materials, Inc.

Inventor： Joseph R. Johnson ,  Christopher Dennis Bencher ,  Thomas L. Laidig

IPC: G03F1/00 ,  G03F1/38 ,  H01L21/027 ,  G03F1/60 ,  G03F1/26

Abstract: Embodiments described herein provide a method shifting mask pattern data during a digital lithography process to reduce line waviness of an exposed pattern. The method includes providing a mask pattern data having a plurality of exposure polygons to a processing unit of a digital lithography system. The processing unit has a plurality of image projection systems that receive the mask pattern data. Each image projection system corresponds to a portion of a plurality of portions of a substrate and receives an exposure polygon corresponding to the portion. The substrate is scanned under the plurality of image projection systems and pluralities of shots are projected to the plurality of portions while shifting the mask pattern data. Each shot of the pluralities of shots is inside the exposure polygon corresponding to the portion.

公开(公告)号：US10509328B2

公开(公告)日：2019-12-17

申请号：US15964986

申请日：2018-04-27

Applicant: Applied Materials, Inc.

Inventor： Christopher Dennis Bencher ,  Joseph R. Johnson

IPC: G03F7/20 ,  G06T7/00

Abstract: Systems and methods discussed herein relate to patterning substrates during lithography and microlithography to form features to a set or sets of critical dimensions using dose. The dose maps are generated based upon images captured during manufacturing to account for process variation in a plurality of operations employed to pattern the substrates. The dose maps are used along with imaging programs to tune the voltages applied to various regions of a substrate in order to produce features to a set or sets of critical dimensions and compensate for upstream or downstream operations that may otherwise result in incorrect critical dimension formation.

公开(公告)号：US10416550B2

公开(公告)日：2019-09-17

申请号：US15936385

申请日：2018-03-26

Applicant: Applied Materials, Inc.

Inventor： Joseph R. Johnson ,  Christopher Dennis Bencher ,  Thomas L. Laidig

IPC: G03F1/38 ,  G03F7/20 ,  G03F1/70

Abstract: Embodiments disclosed herein relate to an exposure pattern alteration software application which manipulates exposure polygons having lines with angles substantially close to angles of symmetry of a hex close pack arrangement, which suffer from long jogs. Long jogs present themselves as high edge placement error regions. As such, the exposure pattern alteration software application provides for line wave reduction by serrating polygon edges at affected angles to reduce edge placement errors during maskless lithography patterning in a manufacturing process.

公开(公告)号：US09927696B2

公开(公告)日：2018-03-27

申请号：US15705771

申请日：2017-09-15

Applicant: Applied Materials, Inc.

Inventor： Joseph R. Johnson ,  Christopher Dennis Bencher ,  Thomas L. Laidig

IPC: G03F1/38 ,  G03F1/70 ,  G03F7/20

CPC classification number: G03F1/38 ,  G03F1/70 ,  G03F7/70291 ,  G03F7/70433 ,  G03F7/70508

Abstract: Embodiments disclosed herein relate to an exposure pattern alteration software application which manipulates exposure polygons having lines with angles substantially close to angles of symmetry of a hex close pack arrangement, which suffer from long jogs. Long jogs present themselves as high edge placement error regions. As such, the exposure pattern alteration software application provides for line wave reduction by serrating polygon edges at affected angles to reduce edge placement errors during maskless lithography patterning in a manufacturing process.

公开(公告)号：US20240045191A1

公开(公告)日：2024-02-08

申请号：US18365853

申请日：2023-08-04

Applicant: Applied Materials, Inc.

Inventor： Ang Li ,  Joseph R. Johnson ,  Jean Marc Fan Chung Tsang Min Ching ,  Dan Xie ,  Stephen Hsiang ,  Yun-Ching Chang

IPC: G02B21/00 ,  G06T7/00 ,  G02B21/06

CPC classification number: G02B21/0076 ,  G06T7/0012 ,  G02B21/06

Abstract: An imaging system for capturing spatial images of biological tissue samples may include an imaging chamber configured to hold a biological tissue sample placed in the imaging system; a light source configured to illuminate the biological tissue sample to activate a plurality of fluorophores in the biological tissue sample; and a plurality of Time Delay and Integration (TDI) imagers configured to simultaneously scan the biological tissue sample, where the plurality of TDI imagers may be configured to separately receive light from different ones of the plurality of fluorophores.

公开(公告)号：US11819847B2

公开(公告)日：2023-11-21

申请号：US16933597

申请日：2020-07-20

Applicant: Applied Materials, Inc.

Inventor： Ryan Scott Smith ,  Roger Quon ,  David Collins ,  George Odlum ,  Raghav Sreenivasan ,  Joseph R. Johnson

IPC: B01L3/00 ,  B82B1/00 ,  B82B3/00 ,  G01N27/447 ,  G01N33/487 ,  G01N27/40

CPC classification number: B01L3/502753 ,  B82B1/005 ,  B82B3/008 ,  G01N27/40 ,  G01N27/44791 ,  G01N33/48721 ,  B01L2200/0647 ,  B01L2300/0896 ,  B01L2300/12

Abstract: Embodiments of the present disclosure provide nanopore devices, such as nanopore sensors and/or other nanofluidic devices. In one or more embodiments, a nanopore device contains a substrate, an optional lower protective oxide layer disposed on the substrate, a membrane disposed on the lower protective oxide layer, and an optional upper protective oxide layer disposed on the membrane. The membrane has a pore and contains silicon nitride. The silicon nitride has a nitrogen to silicon ratio of about 0.98 to about 1.02 and the membrane has an intrinsic stress value of about −1,000 MPa to about 1,000 MPa. The nanopore device also contains a channel extending through at least the substrate, the lower protective oxide layer, the membrane, the upper protective oxide layer, and the upper protective silicon nitride layer.

公开(公告)号：US11325827B2

公开(公告)日：2022-05-10

申请号：US16985959

申请日：2020-08-05

Applicant: Applied Materials, Inc.

Inventor： Philip Allan Kraus ,  Joseph R. Johnson

IPC: B81C1/00 ,  H01L21/02 ,  G01N33/487 ,  G01N27/49 ,  H01L21/302

Abstract: Methods are provided for manufacturing well-controlled, solid-state nanopores and arrays thereof. In one aspect, methods for manufacturing nanopores and arrays thereof exploit a physical seam. One or more etch pits are formed in a topside of a substrate and one or more trenches, which align with the one or more etch pits, are formed in a backside of the substrate. An opening is formed between the one or more etch pits and the one or more trenches. A dielectric material is then formed over the substrate to fill the opening. Contacts are then disposed on the topside and the backside of the substrate and a voltage is applied from the topside to the backside, or vice versa, through the dielectric material to form a nanopore. In another aspect, the nanopore is formed at or near the center of the opening at a seam, which is formed in the dielectric material.

公开(公告)号：US11249067B2

公开(公告)日：2022-02-15

申请号：US16573540

申请日：2019-09-17

Applicant: Applied Materials, Inc.

Inventor： Joseph R. Johnson ,  Roger Quon

IPC: H01L21/00 ,  G01N33/487 ,  B81B1/00 ,  B81C3/00

Abstract: Nanopore flow cells and methods of manufacturing thereof are provided herein. In one embodiment a method of forming a flow cell includes forming a multi-layer stack on a first substrate, e.g., a monocrystalline silicon substrate, before transferring the multi-layer stack to a second substrate, e.g., a glass substrate. Here, the multi-layer stack features a membrane layer, having a first opening formed therethrough, where the membrane layer is disposed on the first substrate, and a material layer is disposed on the membrane layer. The method further includes patterning the second substrate to form a second opening therein and bonding the patterned surface of the second substrate to a surface of the multi-layer stack. The method further includes thinning the first substrate and thinning the second substrate. Here, the second substrate is thinned to where the second opening is disposed therethrough. The method further includes removing the thinned first substrate and at least portions of the material layer to expose opposite surfaces of the membrane layer.