公开(公告)号：US11908678B2

公开(公告)日：2024-02-20

申请号：US17149399

申请日：2021-01-14

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan ,  Joseph Salfelder

IPC: H01L21/02 ,  H01L21/4757

CPC classification number: H01L21/02024 ,  H01L21/02019 ,  H01L21/47573

Abstract: Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.

公开(公告)号：US11586067B2

公开(公告)日：2023-02-21

申请号：US17100407

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  G02F1/1362

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20220223402A1

公开(公告)日：2022-07-14

申请号：US17149399

申请日：2021-01-14

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan ,  Joseph Salfelder

IPC: H01L21/02 ,  H01L21/4757

Abstract: Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.

公开(公告)号：US20220163845A1

公开(公告)日：2022-05-26

申请号：US17100407

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  H01L21/768 ,  G02F1/1362

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20220163707A1

公开(公告)日：2022-05-26

申请号：US17100416

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02B5/08

Abstract: Processing methods may be performed to form a grounded mirror structure on a semiconductor substrate. The methods may include revealing a metal layer. The metal layer may underlie a spacer layer. The metal layer may be revealed by a dry etch process. The method may include forming a mirror layer overlying the spacer layer and the metal layer. The mirror layer may contact the metal layer. The method may also include forming an oxide inclusion overlying a portion of the mirror layer. The portion of the mirror layer may be external to the spacer layer.

公开(公告)号：US20250079357A1

公开(公告)日：2025-03-06

申请号：US18460189

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan ,  Maria Gorchichko ,  Kun Li

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/67

Abstract: A first structure for semiconductor devices having a dielectric film on the top surface can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The top surface of the dielectric film of the first structure can be hybrid bonded to a dielectric layer of a second structure. The dielectric film of the first structure and the dielectric layer of the second structure can be different dielectrics. In this way, the hybrid bonding of the two structures includes the hybrid bonding of asymmetric dielectrics.

公开(公告)号：US12033964B2

公开(公告)日：2024-07-09

申请号：US17411599

申请日：2021-08-25

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Kai Ma ,  Raghav Sreenivasan ,  Jason Appell

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/7684 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/03616 ,  H01L2224/05073 ,  H01L2224/05647 ,  H01L2224/27616 ,  H01L2224/29186

Abstract: Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

公开(公告)号：US11881539B2

公开(公告)日：2024-01-23

申请号：US17100402

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: H01L33/00 ,  H01L33/62 ,  G02F1/1362

CPC classification number: H01L33/0095 ,  G02F1/136277 ,  H01L33/62 ,  H01L2933/0066

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20230369532A1

公开(公告)日：2023-11-16

申请号：US17745056

申请日：2022-05-16

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan

IPC: H01L33/00 ,  H01L25/075

CPC classification number: H01L33/007 ,  H01L25/075 ,  H01L33/32

Abstract: A microLED-quality layer of gallium nitride (GaN) may be formed above a silicon substrate for microLED devices to be formed. Typically, mismatches between the crystal lattice of the GaN and the silicon substrate cause internal stresses that bow the wafer. To relieve these stresses, a pattern of trenches may be etched into the GaN layer between the die or device footprints. These trenches may be etched through the GaN layer, down to the depth of the silicon substrate, or even down into the silicon substrate. Instead of one singular, large wafer with internal stresses, the wafer may thus be divided into multiple small sections with minimal internal stresses. A dielectric gap fill may be applied to fill the trenches, and the resulting wafer may be planarized to expose the surface of the GaN after the gap fill.

公开(公告)号：US20220163846A1

公开(公告)日：2022-05-26

申请号：US17100422

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  H01L21/768 ,  G02F1/1362 ,  H01L23/522

Abstract: Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.