公开(公告)号：US20210055962A1

公开(公告)日：2021-02-25

申请号：US16546752

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Michael David ACHENBACH ,  Robert Greg MCDONALD ,  Nicholas Andrew PFISTER ,  Kelvin Domnic GOVEAS ,  Michael FILIPPO ,  . ABHISHEK RAJA ,  Zachary Allen KINGSBURY

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/52 ,  G06F9/30

Abstract: An apparatus and method are provided for operating an issue queue. The issue queue has a first section and a second section, where each of those sections comprises a number of entries, and where each entry is employed to store operation information identifying an operation to be performed by a processing unit. Allocation circuitry determines, for each item of received operation information, whether to allocate that operation information to an entry in the first section or to an entry in the second section. The operation information identifies not only the associated operation, but also each source operand required by the associated operation and availability of each source operand. Selection circuitry selects from the issue queue, during a given selection iteration, an operation to be issued to the processing unit, and selects that operation from amongst the operations whose required source operands are available. Availability update circuitry is used to update source operand availability for each entry whose operation information identifies as a source operand a destination operand of the selected operation in the given selection iteration. Further, a deferral mechanism is used to inhibit from selection by the selection circuitry, during at least a next selection iteration following the given selection iteration, any operation associated with an entry in the second section whose required source operands are now available due to that operation having as a source operand the destination operand of the selected operation in the given selection iteration. Such an approach can enable the effective capacity of the issue queue to be increased without adversely impacting the timing of the scheduling functionality performed in respect of the issue queue.

公开(公告)号：US20240264841A1

公开(公告)日：2024-08-08

申请号：US18107139

申请日：2023-02-08

Applicant: Arm Limited

Inventor： Glen Andrew HARRIS ,  Alexander Cole SHULYAK ,  . ABHISHEK RAJA ,  Bipin Prasad HEREMAGALUR RAMAPRASAD ,  William Elton BURKY ,  Li MA ,  Michael David ACHENBACH ,  Nicholas Andrew PLANTE ,  Yasuo ISHII

IPC: G06F9/38

CPC classification number: G06F9/3856 ,  G06F9/3861

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

公开(公告)号：US20240126458A1

公开(公告)日：2024-04-18

申请号：US17966071

申请日：2022-10-14

Applicant: Arm Limited

Inventor： Stefano GHIGGINI ,  Natalya Bondarenko ,  Luca NASSI ,  Geoffray Matthieu LACOURBA ,  Huzefa Moiz SANJELIWALA ,  Miles Robert DOOLEY ,  . ABHISHEK RAJA

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.

公开(公告)号：US20240020237A1

公开(公告)日：2024-01-18

申请号：US17864625

申请日：2022-07-14

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Jungsoo KIM ,  James David DUNDAS ,  . ABHISHEK RAJA

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/60

Abstract: There is provided a data processing apparatus in which receive circuitry receives a result signal from a lower level cache and a higher level cache in respect of a first instruction block. The lower level cache and the higher level cache are arranged hierarchically and transmit circuitry transmits, to the higher level cache, a query for the result signal. In response to the result signal originating from the higher level cache containing requested data, the transmit circuitry transmits a further query to the higher level cache for a subsequent instruction block at an earlier time than the further query is transmitted to the higher level cache when the result signal containing the requested data originates from the lower level cache.

公开(公告)号：US20190377599A1

公开(公告)日：2019-12-12

申请号：US16005811

申请日：2018-06-12

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Chris ABERNATHY ,  Michael FILIPPO

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing a plurality of instructions. Storage circuitry stores a plurality of entries, each entry relating to an instruction in the plurality of instructions and including a dependency field. The dependency field stores a data dependency of that instruction on a previous instruction in the plurality of instructions. Scheduling circuitry schedules the execution of the plurality of instructions in an order that depends on each data dependency. When the previous instruction is a single-cycle instruction, the dependency field includes a reference to one of the entries that relates to the previous instruction, otherwise, the data dependency field includes an indication of an output destination of the previous instruction.

公开(公告)号：US20180107606A1

公开(公告)日：2018-04-19

申请号：US15294031

申请日：2016-10-14

Applicant: ARM LIMITED

Inventor： Barry Duane WILLIAMSON ,  Michael FILIPPO ,  . ABHISHEK RAJA ,  Adrian MONTERO ,  Miles Robert DOOLEY

IPC: G06F12/1045 ,  G06F12/128 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/69

Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.

公开(公告)号：US20250068449A1

公开(公告)日：2025-02-27

申请号：US18452622

申请日：2023-08-21

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA

IPC: G06F9/455

Abstract: There is provided an apparatus, system, method, and medium. The apparatus comprises one or more processing elements, each processing element comprising processing circuitry to perform processing operations in one of a plurality of processing contexts. Each processing element further comprises context tracking circuitry to store context tracking data indicative of active contexts. Each processing element comprises control circuitry responsive to a request for a memory synchronisation occurring subsequent to at least one maintenance operation associated with a given set of one or more contexts of the plurality of processing contexts, to determine whether the at least one of the given set of one or more contexts is indicated in the context tracking data. The control circuitry is configured, when the at least one of the given set of one or more contexts is determined to be indicated in the context tracking data, to implement a delay before performing the memory synchronisation, and when each of the given set of one or more contexts is determined to be absent from the context tracking data, to perform the memory synchronisation without implementing the delay.

公开(公告)号：US20240143510A1

公开(公告)日：2024-05-02

申请号：US17978400

申请日：2022-11-01

Applicant: Arm Limited

Inventor： Anton SMEKALOV ,  . ABHISHEK RAJA

IPC: G06F12/0891

CPC classification number: G06F12/0891 ,  G06F2212/604

Abstract: There is provided an apparatus, medium and method for cache invalidation. The apparatus comprises a cache having a plurality of entries grouped into a plurality of entry sets. Each entry of the plurality of entries identifies an address range having one of a plurality of predetermined address range sizes. The apparatus further comprises cache invalidation circuitry responsive to a cache invalidation request indicating an address invalidation range to trigger invalidation of entries in the cache that overlap the address invalidation range. The cache invalidation circuitry is configured to operate in one of a plurality of invalidation modes based on the address invalidation range and cache occupancy information indicating address range sizes identified by the plurality of entries in the cache. The plurality of invalidation modes comprise: an entry-driven invalidation mode in which the cache invalidation circuitry is configured, for each entry of the plurality of entries and in response to a determination that the address invalidation range overlaps the address range identified by that entry, to invalidate that entry; and an invalidation-range-driven invalidation mode in which the cache invalidation circuitry is configured to generate a set of address range sizes based on the address range sizes indicated in the cache occupancy information and, for each given address range size, to generate one or more cache indexes from the address invalidation range in dependence on the given address range size, each of the cache indexes identifying a corresponding entry set of the plurality of entry sets, and for each corresponding entry set to invalidate entries in dependence on whether the address range identified by those entries overlaps the address invalidation range.

公开(公告)号：US20230289092A1

公开(公告)日：2023-09-14

申请号：US17693817

申请日：2022-03-14

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Balaji VIJAYAN ,  Alexander Cole SHULYAK

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0673

Abstract: An apparatus comprises processing circuitry to issue store operations to store data to a data store and load operations to load data from the data store and a store buffer comprising entries to store entry information corresponding to store operations in advance of the store operations completing. Store buffer lookup circuitry is provided to lookup, in response to a load operation, whether the store buffer contains a corresponding entry corresponding to an older store operation for which target addresses of the load operation and the older store operation satisfy an address comparison condition. The store buffer lookup circuitry is configured to perform store-to-load forwarding in response to the load operation when the corresponding entry is a first type of store buffer entry satisfying a forwarding condition, and delay processing of the load operation when the corresponding entry is a second type of store buffer entry satisfying the forwarding condition.

公开(公告)号：US20230176979A1

公开(公告)日：2023-06-08

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Joseph Michael PUSDESRIS ,  . ABHISHEK RAJA ,  Karthik SUNDARAM ,  Anoop Ramachandra IYER ,  Michael Brian SCHINZLER ,  James David DUNDAS ,  Yasuo ISHII

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.