公开(公告)号：US09632955B2

公开(公告)日：2017-04-25

申请号：US14628335

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Arthur Laughton ,  Andrew David Tune ,  Daniel Sara

IPC: G06F13/16 ,  G06F12/08 ,  G06F12/0831

CPC classification number: G06F13/1626 ,  G06F12/0831 ,  G06F13/1642 ,  G06F2212/621

Abstract: A system-on-chip integrated circuit 2 includes interconnect circuitry 4 for communicating transactions between transaction sources and transaction destinations. A reorder buffer 26 serves to buffer and permit reordering of access transactions received from the transaction sources. Processing circuitry performs processing operations in parallel upon a given access transaction taken from the reorder buffer. Hazard detection and repair circuitry serves to detect an ordering hazard arising between the processing operations and if necessary cancel and repeat that processing operation. The access transactions and the reorder buffer are such that access transactions other than the access transaction for which a hazard has been detected may proceed independently of the necessity to cancel and repair that transaction thereby reducing the cost associated with cancelling and repair.

公开(公告)号：US09507716B2

公开(公告)日：2016-11-29

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Jamshed Jalal ,  Mark David Werkheiser ,  Arthur Laughton ,  George Robert Scott Lloyd ,  Peter Andrew Riocreux ,  Daniel Sara

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。

公开(公告)号：US08819309B1

公开(公告)日：2014-08-26

申请号：US13918023

申请日：2013-06-14

Applicant: ARM Limited

Inventor： Alistair Crone Bruce ,  Andrew David Tune

IPC: G06F13/38 ,  G06F3/06

CPC classification number: G06F13/385

Abstract: Buffer circuitry 14 is provided with shared buffer circuitry 20 which stores, in order of reception time, data transaction requests received from one or more data transaction sources. The buffer circuitry 14 operates in either a bypass mode or a non-bypass mode. When operating in the bypass mode, any low latency data transaction requests stored within the shared buffer circuitry are selected in order for output in preference to data transaction requests that are not low latency data transaction requests. In the non-bypass mode, transactions (whether or not they are low latency transactions) are output from the shared buffer circuitry 20 in accordance with the order in which they are received into the shared buffer circuitry 20. The switch between the bypass mode and the non-bypass mode is made in dependence upon comparison of a detected rate of output of low latency data transaction requests compared to a threshold value. If the rate exceeds the threshold value, then the switch is made to the non-bypass mode so that data transaction requests which are not low latency data transaction requests are permitted a fair share of the output bandwidth.

Abstract translation: 缓冲电路14设置有共享缓冲器电路20，其以接收时间的顺序存储从一个或多个数据事务源接收的数据事务请求。 缓冲电路14以旁路模式或非旁路模式工作。 当在旁路模式下操作时，选择存储在共享缓冲器电路中的任何低延迟数据事务请求，以优先于不是低延迟数据事务请求的数据事务请求进行输出。 在非旁路模式中，事务（不管它们是否是低延迟事务）根据它们被接收到共享缓冲电路20中的顺序从共享缓冲器电路20输出。旁路模式和 根据与阈值相比较的低等待时间数据事务请求的检测速率的比较，进行非旁路模式。 如果速率超过阈值，则将交换机变为非旁路模式，使得不是低延迟数据事务请求的数据事务请求被允许输出带宽的公平共享。

公开(公告)号：US12181967B2

公开(公告)日：2024-12-31

申请号：US18119389

申请日：2023-03-09

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Cyrille Nicolas Dray

IPC: G06F11/10

Abstract: Data storage circuitry has entries to store data according to a data storage technology supporting non-destructive reads, each entry associated with an error checking code (ECC) and age indication. Scrubbing circuitry performs a patrol scrubbing cycle to visit each entry of the data storage circuitry within a scrubbing period. On a given visit to a given entry, the scrubbing operation comprises determining, based on the age indication associated with the given entry, whether a check-not-required period has elapsed for the given entry, and if so performing an error check on the data of the given entry using the ECC for that entry. The error check is omitted if the check-not-required period has not yet elapsed. The check-not-required period is restarted for a write target entry in response to a request causing an update to the data and the error checking code of the write target entry. The check-not-required period is restarted for a read target entry in response to a request causing the data of a read target entry to be non-destructively read and subject to the error check.

公开(公告)号：US11314675B2

公开(公告)日：2022-04-26

申请号：US16659762

申请日：2019-10-22

Applicant: Arm Limited

Inventor： Guanghui Geng ,  Andrew David Tune ,  Daniel Adam Sara ,  Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  G06F12/0888 ,  G06F12/0815

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

公开(公告)号：US10929060B2

公开(公告)日：2021-02-23

申请号：US16037091

申请日：2018-07-17

Applicant: Arm Limited

Inventor： Andrew David Tune

IPC: G06F3/06 ,  G06F12/06

Abstract: An integrated circuit comprises: a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion, and a control node responsive to the data access request to control at least one destination node to service at least one data access transaction. Each data access transaction is associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.

公开(公告)号：US10740269B2

公开(公告)日：2020-08-11

申请号：US16037117

申请日：2018-07-17

Applicant: Arm Limited

Inventor： Andrew David Tune

IPC: G06F12/00 ,  G06F13/366 ,  G06F9/50

Abstract: Arbitration circuitry is provided for allocating up to M resources to N requesters, where M≥2. The arbitration circuitry comprises group allocation circuitry to control a group allocation in which the N requesters are allocated to M groups of requesters, with each requester allocated to one of the groups; and M arbiters each corresponding to a respective one of the M groups. Each arbiter selects a winning requester from the corresponding group, which is to be allocated a corresponding resource of the M resources. In response to a given requester being selected as the winning requester by the arbiter for a given group, the group allocation is changed so that in a subsequent arbitration cycle the given requester is in a different group to the given group.

公开(公告)号：US09892072B2

公开(公告)日：2018-02-13

申请号：US14874801

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Arthur Brian Laughton ,  Daniel Adam Sara ,  Sean James Salisbury ,  Peter Andrew Riocreux

IPC: G06F13/00 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/4282

Abstract: Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.

公开(公告)号：US09727466B2

公开(公告)日：2017-08-08

申请号：US14822953

申请日：2015-08-11

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Sean James Salisbury

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0808

CPC classification number: G06F12/0833 ,  G06F12/0808 ,  G06F12/0831 ,  G06F2212/62 ,  G06F2212/621 ,  Y02D10/13

Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage. The coherency control circuitry then responds to the snoop control data by issuing a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data. Analysis circuitry then determines from the snoop response data an update condition, and upon detection of the update condition triggers performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data. By subjecting the snoop response data to such an analysis, it is possible to identify situations where the caching indication data has become out of date, and update that caching indication data accordingly, this giving rise to significant performance benefits in the operation of the interconnect.

公开(公告)号：US09361236B2

公开(公告)日：2016-06-07

申请号：US13920685

申请日：2013-06-18

Applicant: ARM Limited

Inventor： Andrew David Tune ,  Sean James Salisbury

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0846

Abstract: A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways.

Abstract translation: 数据阵列有多种方式，每种方式都有用于存储数据值的条目。 响应于写请求，具有目标地址的更新的数据值可以存储在包括从每个方式基于目标地址选择的条目的对应的一组条目中的任何一个中。 更新队列存储表示待决写入请求的更新信息。 对于与不同方式相对应的一组待决写入请求，从更新队列中选择更新信息，并且并行执行这些写请求，使得更新的值被写入不同方式的条目。