公开(公告)号：US20240055047A1

公开(公告)日：2024-02-15

申请号：US17885709

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Edward Martin McCombs, JR. ,  Andrew David Tune ,  Sean James Salisbury ,  Rahul Mathur ,  Hsin-Yu Chen ,  Phani Raja Bhushan Chalasani

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

公开(公告)号：US10177760B1

公开(公告)日：2019-01-08

申请号：US15636428

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Yicong Li ,  Hsin-Yu Chen ,  Sriram Thyagarajan

IPC: G11C5/06 ,  H03K17/687 ,  G11C5/14 ,  H01L23/64 ,  G11C7/10 ,  G06F17/50 ,  G11C8/08

Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.

公开(公告)号：US11017142B1

公开(公告)日：2021-05-25

申请号：US17010630

申请日：2020-09-02

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Shruti Aggarwal ,  Mohit Chanana ,  Hsin-Yu Chen ,  Kyung Woo Kim

IPC: G06F30/343 ,  G06F30/337 ,  G06F30/20 ,  G06F1/28 ,  G06F119/12 ,  G06F119/06 ,  G06F30/3308

Abstract: According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.

公开(公告)号：US20190007043A1

公开(公告)日：2019-01-03

申请号：US15636428

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Yicong Li ,  Hsin-Yu Chen ,  Sriram Thyagarajan

IPC: H03K17/687 ,  G11C5/14 ,  G11C8/08 ,  G11C7/10 ,  G06F17/50 ,  H01L23/64

Abstract: A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.

公开(公告)号：US20180342271A1

公开(公告)日：2018-11-29

申请号：US15603252

申请日：2017-05-23

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rahul Mathur ,  Abhishek Baradia ,  Hsin-Yu Chen

IPC: G11C7/12 ,  G11C7/22

CPC classification number: G11C8/10 ,  G11C8/06

Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.

公开(公告)号：US09627022B2

公开(公告)日：2017-04-18

申请号：US14836657

申请日：2015-08-26

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Hsin-Yu Chen ,  Sabarish Ittamveetil ,  Yew Keong Chong ,  Indranil Basu ,  Vikash

IPC: G11C8/18 ,  G11C5/02 ,  G11C7/22 ,  G11C7/10 ,  G11C8/12 ,  G11C7/06 ,  G06F13/28

CPC classification number: G11C8/18 ,  G06F13/28 ,  G11C5/025 ,  G11C7/062 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/12

Abstract: A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal.