公开(公告)号：US07989362B2

公开(公告)日：2011-08-02

申请号：US12505963

申请日：2009-07-20

申请人： Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

发明人： Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

IPC分类号： H01L21/20 ,  H01L23/62 ,  H01L27/108 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L21/02194 ,  C23C16/308 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/3145 ,  H01L21/31645 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.

摘要翻译： 形成电子设备的电子设备和方法包括用于各种电子系统的基板上的铪镧系元素氮氧化物膜。 铪镧系氮氧化物膜可以构成为一个或多个单层。 金属电极可以设置在含有铪镧系元素氮氧化物膜的电介质上。

公开(公告)号：US07898850B2

公开(公告)日：2011-03-01

申请号：US11871339

申请日：2007-10-12

申请人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

发明人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

摘要翻译： 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

公开(公告)号：US07875529B2

公开(公告)日：2011-01-25

申请号：US11867733

申请日：2007-10-05

申请人： Leonard Forbes ,  Paul A. Farrar ,  Arup Bhattacharyya ,  Hussein I. Hanafi ,  Warren M. Farnworth

发明人： Leonard Forbes ,  Paul A. Farrar ,  Arup Bhattacharyya ,  Hussein I. Hanafi ,  Warren M. Farnworth

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L25/18 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/092 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2225/06513 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01056 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/00

摘要： Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.

摘要翻译： 本文描述了在堆叠晶片系统中提供半导体器件的方法，器件，模块和系统。 一个实施例包括用于CMOS架构中的NMOS晶体管的第一晶片和用于CMOS结构中的PMOS晶体管的第二晶片，其中第一晶片被结合并电耦合到第二晶片以形成至少一个CMOS器件。 另一个实施例包括形成在第一晶片上的多个DRAM电容器和与形成在第二晶片上的DRAM电容器相关联的支持电路，其中第一晶片被接合并电耦合到第二晶片以形成多个DRAM单元。 另一实施例包括具有耦合到数据线的多个垂直晶体管的第一晶片和具有与多个垂直晶体管相关联的放大器电路的第二晶片，其中第一晶片被接合并电耦合到第二晶片。

公开(公告)号：US07829938B2

公开(公告)日：2010-11-09

申请号：US11181345

申请日：2005-07-14

申请人： Arup Bhattacharyya

发明人： Arup Bhattacharyya

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0475 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/42336 ,  H01L29/513 ,  H01L29/7881

摘要： Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate-stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.

摘要翻译： 描述了利用双栅极（或背侧栅极）非易失性存储器单元的非易失性存储器件和阵列，其具有放置在前侧或后侧电荷俘获中的沟道区域的上方或下方的带工程化栅极堆叠 NAND存储器阵列架构中的栅极堆叠配置。 具有本发明实施例的浮动节点存储器单元的不对称或直接隧道势垒的带隙工程化栅极堆栈允许低电压隧道编程和电子和空穴的有效擦除，同时保持高电荷阻挡屏障和深载流子俘获 网站保持良好的电荷。 存储单元架构还允许利用减少的特征字线和垂直选择栅极的改进的高密度存储器件或阵列。

公开(公告)号：US20100193032A1

公开(公告)日：2010-08-05

申请号：US12757870

申请日：2010-04-09

申请人： Arup Bhattacharyya

发明人： Arup Bhattacharyya

IPC分类号： H01L31/0264

CPC分类号： H01L31/022425 ,  H01L31/0264 ,  H01L31/062 ,  H01L31/0725 ,  H01L31/1085 ,  Y02E10/50

摘要： The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.

摘要翻译： 本发明包括含有一层或多层半导体富集绝缘体（富含富硅的绝缘体为富硅氧化硅和富含硅的氮化硅）的光电器件，并且包括含有一层或多层半导体富集绝缘体的太阳能电池 。 本发明还包括形成光电器件和太阳能电池的方法。

公开(公告)号：US20100072537A1

公开(公告)日：2010-03-25

申请号：US12623895

申请日：2009-11-23

申请人： Arup Bhattacharyya

发明人： Arup Bhattacharyya

IPC分类号： H01L29/792

CPC分类号： H01L29/42332 ,  B82Y10/00 ,  G11C16/0416 ,  G11C16/0483 ,  G11C2216/06 ,  H01L29/513 ,  H01L29/7883

摘要： Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

摘要翻译： 描述了使用具有带工程化栅极堆叠的反向模式非易失性存储器单元和在EEPROM和块可擦除存储器件（例如闪存器件）中的纳米晶体电荷俘获的非易失性存储器件和阵列。 本发明的实施例允许使用控制门的反向模式栅极 - 绝缘体堆叠存储器单元来编程和擦除通过波段设计的波峰隧道势垒。 通过在非导电捕获层和高K介电电荷阻挡层中利用高功函数纳米晶体来提高电荷保持率。 具有本发明实施例的非易失性存储单元的具有对称或非对称顶点势垒隧道层的带隙工程的栅极叠层允许用电子和空穴进行低电压隧道编程和擦除，同时保持高电荷阻挡屏障和深度 载体捕获位点，保持良好的电荷。

公开(公告)号：US07660144B2

公开(公告)日：2010-02-09

申请号：US11477315

申请日：2006-06-28

申请人： Arup Bhattacharyya

发明人： Arup Bhattacharyya

IPC分类号： G11C17/06

CPC分类号： H01L27/108 ,  G11C11/40 ,  G11C11/404 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： A memory cell embodiment includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode.

摘要翻译： 存储单元实施例包括具有浮动节点的存取晶体管和连接在浮动节点和二极管参考电位线之间的二极管。 二极管包括阳极，阴极和阳极和阴极之间的本征区域。 表示存储单元的存储状态的电荷被保持在二极管的本征区域的两侧。

公开(公告)号：US07625803B2

公开(公告)日：2009-12-01

申请号：US11348571

申请日：2006-02-06

申请人： Arup Bhattacharyya

发明人： Arup Bhattacharyya

IPC分类号： H01L21/8222

CPC分类号： H01L27/10852 ,  G11C11/404 ,  H01L21/84 ,  H01L27/10817 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/55

摘要： The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a reference plate which splits into at least two prongs. Each of the prongs is surrounded by a lateral periphery. A dielectric material extends around the lateral peripheries of the prongs, and a storage node surrounds an entirety of the lateral peripheries of the prongs. The storage node is separated from the reference plate by at least the dielectric material. Also, the invention includes electronic systems comprising novel capacitor constructions.

摘要翻译： 本发明包括具有与晶体管组合的电容器的存储器件。 存储器件可以在TFT结构内。 电容器被配置为提供用于电容增强的电容的面积和周边分量。 该电容器包括分为至少两个插脚的参考板。 每个尖头被一个外围包围。 介电材料围绕插脚的外周延伸，并且存储节点围绕插脚的整个外围。 存储节点通过至少介电材料与参考板分离。 此外，本发明包括包括新颖的电容器结构的电子系统。

公开(公告)号：US07605030B2

公开(公告)日：2009-10-20

申请号：US11515114

申请日：2006-08-31

申请人： Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

发明人： Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

IPC分类号： H01L21/338 ,  H01L21/336

CPC分类号： G11C16/0466 ,  H01L21/3142 ,  H01L21/31637 ,  H01L21/31645 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545

摘要： Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.

摘要翻译： 电子设备和方法可以包括用于各种电子系统的基板上的铪钽氮化物膜。 铪钽氮氧化物膜可以被构造为一个或多个单层。 可以使用原子层沉积形成氮氧化钽铪膜。 金属电极可以设置在含有铪钽氮氧化物膜的电介质上。

公开(公告)号：US20090256243A1

公开(公告)日：2009-10-15

申请号：US12475896

申请日：2009-06-01

申请人： Joseph E. Geusic ,  Paul A. Farrar ,  Arup Bhattacharyya

发明人： Joseph E. Geusic ,  Paul A. Farrar ,  Arup Bhattacharyya

IPC分类号： H01L23/00 ,  H01B17/36

CPC分类号： H01L21/0212 ,  H01L21/02145 ,  H01L21/02161 ,  H01L21/02203 ,  H01L21/02266 ,  H01L21/02354 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/3122 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.

摘要翻译： 提供系统，器件和方法，以通过提供低k绝缘体来提高集成电路的性能。 一个方面是集成电路绝缘体结构。 一个实施例包括绝缘体材料的固体结构，以及形成在固体结构内的至少一个空隙的精确确定的布置，其降低绝缘体结构的有效介电常数。 一个方面是形成低k绝缘体结构的方法。 在一个实施例中，沉积绝缘体材料，并且在绝缘体材料的表面中形成至少一个孔的预定布置。 绝缘体材料被退火，使得低k电介质材料进行表面变换，以将至少一个孔的布置转换成绝缘体材料表面下方的至少一个空白空间的预定布置。 本文提供了其他方面。