公开(公告)号：US06735110B1

公开(公告)日：2004-05-11

申请号：US10125666

申请日：2002-04-17

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C1100

CPC分类号： G11C11/4125

摘要： Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

公开(公告)号：US06445238B1

公开(公告)日：2002-09-03

申请号：US09452234

申请日：1999-12-01

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03H1126

CPC分类号： H03H11/265 ,  H03K2005/00143

摘要： The supply voltage to which a delay circuit's buffer stages are coupled is adjusted in response to changes in temperature according to a predetermined relationship to maintain a substantially constant buffer stage gate delay over temperature variations. Decreasing gate delays resulting from decreases in temperature are offset by decreasing the supply voltage, which in turn increases gate delays. Conversely, increasing gate delays resulting from increases in temperature are offset by increasing the supply voltage, which in turn decreases gate delays. In some embodiments, a control circuit is connected to the reference voltage circuit that supplies VCC to the delay circuit, and adjusts VCC in response to temperature to maintain substantially constant gate delay over temperature. In one embodiment, the control circuit includes a microprocessor and a look-up table containing desired supply voltage versus temperature mappings. In another embodiment, the control circuit is formed as part of an existing bandgap reference circuit associated with the reference voltage circuit, and therefore consumes minimal silicon area.

摘要翻译： 响应于根据预定关系的温度变化来调节延迟电路的缓冲级耦合到的电源电压，以保持在温度变化上基本恒定的缓冲级门延迟。 通过降低电源电压来抵消由温度降低导致的门延迟的降低，这进而增加了门延迟。 相反，由于温度升高引起的栅极延迟增加可通过增加电源电压来抵消，这进而降低了栅极延迟。 在一些实施例中，控制电路连接到将VCC提供给延迟电路的参考电压电路，并且响应于温度来调节VCC以在温度上保持基本恒定的门延迟。 在一个实施例中，控制电路包括微处理器和包含期望的电源电压对温度映射的查找表。 在另一个实施例中，控制电路形成为与参考电压电路相关联的现有带隙参考电路的一部分，因此消耗最小的硅面积。

公开(公告)号：US06351145B1

公开(公告)日：2002-02-26

申请号：US09827615

申请日：2001-04-06

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03K19177

CPC分类号： H03M1/004 ,  H03M1/365 ,  H03M1/46

摘要： An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC. In some embodiments, an interface cell has a pad that is usable for receiving a digital signal or for receiving an analog signal. The interface cell includes special dedicated analog circuitry that has a differential input lead that is programmably couplable to the pad.

摘要翻译： 模数转换器（ADC）在现场可编程门阵列（FPGA）中实现，而无需添加特殊的专用模拟电路。 在数字应用中，FPGA的接口单元中的比较器将输入的数字信号与参考电压进行比较。 调整参考电压允许接口单元支持不同的数字I / O标准。 在一个实施例中，比较器不用于该数字目的，而是用作ADC中的比较器。 闪存ADC通过使用大量接口单元的比较器作为闪存ADC的比较器来实现。 通过降低模拟信号输入路径的阻抗来提高转换速度。 提供片上电阻串，使闪存ADC无需外部元件即可实现。 在另一个实施例中，接口单元的比较器是逐次逼近ADC的比较器。 在一些实施例中，接口单元具有可用于接收数字信号或用于接收模拟信号的焊盘。 接口单元包括专用的专用模拟电路，其具有可编程地耦合到焊盘的差分输入引线。

公开(公告)号：US06204815B1

公开(公告)日：2001-03-20

申请号：US09302587

申请日：1999-04-30

申请人： Austin H. Lesea ,  Robert O. Conn

发明人： Austin H. Lesea ,  Robert O. Conn

IPC分类号： H01Q138

CPC分类号： H01Q21/0037 ,  H01Q1/38

摘要： The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit. Antenna/receiver circuit pairs are disposed at various locations across the surface of the integrated circuit where the signal is to be received and used. Other methods and embodiments are disclosed.

摘要翻译： 在集成电路中的导体上行进的电信号的最大传播速度受到围绕导体的电介质材料的介电常数的限制。 不是通过介电常数为两个或两个以上的介电材料包围的导体传输电信号，而是以跨越整个集成电路表面的高速通过空气传播信号作为电磁波。 在一个实施例中，射频（RF）信号经由传输线路传递到集成电路封装中。 传输线将RF信号提供给设置在封装内的集成电路上方的波导状结构。 RF信号通过波导结构中的空气通过集成电路的上表面传播作为电磁波。 天线/接收器电路对设置在集成电路的要被接收和使用信号的表面的各个位置处。 公开了其它方法和实施例。

公开(公告)号：US08549379B2

公开(公告)日：2013-10-01

申请号：US12950171

申请日：2010-11-19

申请人： Alfred L. Rodriguez ,  Nicholas J. Possley ,  Kevin Boshears ,  Austin H. Lesea ,  Jameel Hussein

发明人： Alfred L. Rodriguez ,  Nicholas J. Possley ,  Kevin Boshears ,  Austin H. Lesea ,  Jameel Hussein

IPC分类号： G06F11/00

CPC分类号： G06F11/106

摘要： Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit.

摘要翻译： 方法和系统减轻了集成电路中的软错误。 映射存储在存储器中，映射指定集成电路中每个存储位的关键等级。 缓解技术与每个临界级相关联。 在损坏的一个存储位中检测到软错误。 执行缓解技术，其与映射中为损坏的存储位指定的关键等级相关联。

公开(公告)号：US20120131417A1

公开(公告)日：2012-05-24

申请号：US12950171

申请日：2010-11-19

申请人： Alfred L. Rodriguez ,  Nicholas J. Possley ,  Kevin Boshears ,  Austin H. Lesea

发明人： Alfred L. Rodriguez ,  Nicholas J. Possley ,  Kevin Boshears ,  Austin H. Lesea

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/106

摘要： Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit.

摘要翻译： 方法和系统减轻了集成电路中的软错误。 映射存储在存储器中，映射指定集成电路中每个存储位的关键等级。 缓解技术与每个临界级相关联。 在损坏的一个存储位中检测到软错误。 执行缓解技术，其与映射中为损坏的存储位指定的关键等级相关联。

公开(公告)号：US08014184B1

公开(公告)日：2011-09-06

申请号：US12558770

申请日：2009-09-14

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C5/06

CPC分类号： H03K19/00338 ,  G11C11/412

摘要： A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is coupled between a data node and the second address transistor, and the second address transistor is coupled between the first address transistor and the data value storage circuit. The first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and the second address transistor well is coupled to a ground terminal.

摘要翻译： 存储单元具有数据值存储电路和数据地址电路，其包括形成在第一地址晶体管阱中的第一地址晶体管和形成在第二地址晶体管阱中的第二地址晶体管。 第一地址晶体管耦合在数据节点和第二地址晶体管之间，第二地址晶体管耦合在第一地址晶体管和数据值存储电路之间。 第一地址晶体管阱耦合到第一地址晶体管和第二地址晶体管之间的中间节点，并且第二地址晶体管阱耦合到接地端子。

公开(公告)号：US07505542B1

公开(公告)日：2009-03-17

申请号：US11195544

申请日：2005-08-01

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03D3/24

CPC分类号： H03C3/09 ,  H03L7/085 ,  H03L7/0996

摘要： A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein an average rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates a modulated error value based on the snapshots and a modulation value, where the modulation value is used to spread the spectrum of the output clock. The tapped delay line module produces the output clock based on the modulated error value.

摘要翻译： 低抖动数字频率合成器包括第一计数器模块，第二计数器模块，快照模块，误差值生成模块和抽头延迟线。 第一计数器模块计算输入时钟的M个周期的间隔以产生第一计数。 第二计数器模块计数输出时钟的D个周期的间隔以产生第二计数，其中输出时钟的平均速率对应于输入时钟的速率的M / D倍。 快照模块定期拍摄第一和第二个计数的快照，以生成快照。 误差值生成模块基于快照和调制值生成调制误差值，其中调制值用于扩展输出时钟的频谱。 抽头延迟线模块基于调制的误差值产生输出时钟。

公开(公告)号：US07437633B1

公开(公告)日：2008-10-14

申请号：US10402837

申请日：2003-03-27

申请人： Austin H. Lesea ,  Yiding Wu

发明人： Austin H. Lesea ,  Yiding Wu

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31715 ,  G01R31/31726

摘要： Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.

摘要翻译： 描述了在输入/输出节点处测试占空比的方法和装置。 产生具有非零频率和占空比的测试信号。 使用采样信号对测试信号进行采样。 采样信号的相位被移位以检测采样的测试信号中的第一电平变化。 然后移位采样信号的相位以检测采样的测试信号中的第二电平变化。 使用在第一电平变化时的采样信号的相位指示器来计算测试信号的占空比，并且在第二电平改变时采样信号的相位指示符。

公开(公告)号：US07088172B1

公开(公告)日：2006-08-08

申请号：US10360465

申请日：2003-02-06

申请人： Austin H. Lesea ,  Patrick J. Crotty

发明人： Austin H. Lesea ,  Patrick J. Crotty

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G05F3/205

摘要： A configurable voltage bias circuit is used to control gate delays in buffers by adjusting the supply voltage of the buffers. The programmable voltage bias circuit includes a configurable voltage divider, which receives an input supply voltage and generates an output supply voltage, and a configurable resistance circuit, which is coupled between the configurable voltage divider and ground. By using a temperature dependent reference voltage to generate the input supply voltage, the output supply voltage is also made to be dependent upon temperature. The programmable voltage bias circuit of the present invention uses the temperature dependence of the output supply voltage to make the gate delays of the buffer temperature-independent.

摘要翻译： 可配置的电压偏置电路用于通过调节缓冲器的电源电压来控制缓冲器中的栅极延迟。 可编程电压偏置电路包括可配置的分压器，其接收输入电源电压并产生输出电源电压，以及耦合在可配置分压器和地之间的可配置电阻电路。 通过使用与温度相关的参考电压来产生输入电源电压，输出电源电压也取决于温度。 本发明的可编程电压偏置电路使用输出电源电压的温度依赖性使缓冲器的栅极延迟与温度无关。