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303 条记录 (耗时 0.035 秒)

    Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers
    12.
    发明授权
    Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers 有权
    通过原子层外延原位δ掺杂掺杂剂扩散阻挡层的突变结形成

    公开(公告)号：US07485536B2

    公开(公告)日：2009-02-03

    申请号：US11326178

    申请日：2005-12-30

    申请人： Been-Yih Jin ,  Brian S. Doyle ,  Robert S. Chau ,  Jack T. Kavalieros

    发明人： Been-Yih Jin ,  Brian S. Doyle ,  Robert S. Chau ,  Jack T. Kavalieros

    IPC分类号： H01L21/335

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

    摘要： A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.

    摘要翻译： 一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。 一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。 一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及衬底的阱和沟道区之间的阻挡层。

    Tri-gate patterning using dual layer gate stack
    14.
    发明授权
    Tri-gate patterning using dual layer gate stack 有权
    使用双层栅极堆叠的三栅极图案化

    公开(公告)号：US07745270B2

    公开(公告)日：2010-06-29

    申请号：US12006047

    申请日：2007-12-28

    申请人： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    发明人： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

    摘要翻译： 通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。 在衬底上形成高介电常数层。 在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。 在第一和第二功函数金属层上形成硅锗层。 在硅锗层上形成多晶硅层并进行抛光。 第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。 硬掩模被图案化并用于蚀刻多晶硅层和硅锗层以产生栅极堆叠。 硅锗层的蚀刻速率比第一功函数金属层更快。

    Tri-gate patterning using dual layer gate stack
    16.
    发明申请
    Tri-gate patterning using dual layer gate stack 有权
    使用双层栅极堆叠的三栅极图案化

    公开(公告)号：US20090170267A1

    公开(公告)日：2009-07-02

    申请号：US12006047

    申请日：2007-12-28

    申请人： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    发明人： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A ploysilicon layer is formed over the silicon germanium layer and is polished. The ploysilicon layer over the first work function metal layer is thicker than the ploysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the ploysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

    摘要翻译： 通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。 在衬底上形成高介电常数层。 在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。 在第一和第二功函数金属层上形成硅锗层。 在硅锗层上方形成硅层，并进行抛光。 第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。 硬掩模被图案化并用于蚀刻合金层和硅锗层以产生栅极堆叠。 硅锗层的蚀刻速率比第一功函数金属层更快。

    Substrate band gap engineered multi-gate pMOS devices
    17.
    发明授权
    Substrate band gap engineered multi-gate pMOS devices 有权
    基板带隙工程多栅极pMOS器件

    公开(公告)号：US08169027B2

    公开(公告)日：2012-05-01

    申请号：US12757917

    申请日：2010-04-09

    申请人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta

    发明人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta

    IPC分类号： H01L29/66

    CPC分类号： H01L29/78687 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78609

    摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

    摘要翻译： 多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。 所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。 多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

    SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES
    18.
    发明申请
    SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES 有权
    基板带隙工程多栅极PMOS器件

    公开(公告)号：US20100193840A1

    公开(公告)日：2010-08-05

    申请号：US12757917

    申请日：2010-04-09

    申请人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta

    发明人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta

    IPC分类号： H01L27/088

    CPC分类号： H01L29/78687 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78609

    摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

    摘要翻译： 多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。 所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。 多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。