公开(公告)号：US20100001370A1

公开(公告)日：2010-01-07

申请号：US12168816

申请日：2008-07-07

申请人： Haifeng Sheng ,  Fan Zhang ,  Juan Boon Tan ,  Bei Chao Zhang ,  Dong Kyun Sohn

发明人： Haifeng Sheng ,  Fan Zhang ,  Juan Boon Tan ,  Bei Chao Zhang ,  Dong Kyun Sohn

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L27/06

CPC分类号： H01L23/5223 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.

摘要翻译： 一种集成电路系统，包括：提供包括前端电路的基板; 形成包括在所述衬底上的第一导电迹线的第一导电电平; 形成与所述第一导电电平间隔开并包括第二导电迹线的第二导电电平; 以及将第一导电电平与通过第二导电电平而不接触第二导电迹线的viabar连接到第三导电电平。

公开(公告)号：US20090085122A1

公开(公告)日：2009-04-02

申请号：US11865563

申请日：2007-10-01

申请人： Vincent Ho ,  Wenhe Lin ,  Young Way Teh ,  Yong Kong Siew ,  Bei Chao Zhang ,  Fan Zhang ,  Haifeng Sheng ,  Juan Boon Tan

发明人： Vincent Ho ,  Wenhe Lin ,  Young Way Teh ,  Yong Kong Siew ,  Bei Chao Zhang ,  Fan Zhang ,  Haifeng Sheng ,  Juan Boon Tan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

摘要翻译： 本发明提供了一种通过在源/漏退火处理之前将栅极区域施加离子注入来在半导体器件衬底中引起应力的方法。 然后可以将栅极/漏极区域与栅极退火，由于所述离子注入将导致栅极在某些区域中膨胀。 结果，由栅极的所述膨胀引起的应力被转移到半导体衬底中的沟道区域。

公开(公告)号：US06403478B1

公开(公告)日：2002-06-11

申请号：US09651966

申请日：2000-08-31

申请人： Chim-Seng Seet ,  Chyi Shyuam Chern ,  Juan Boon Tan

发明人： Chim-Seng Seet ,  Chyi Shyuam Chern ,  Juan Boon Tan

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76877

摘要： A new method for preventing intermittent high Kelvin via resistance is achieved. This is accomplished by lowering the chamber pressure during warm-up, which prevents the wafer temperature from rising above about 380° C. The present invention uses a pressure of between 2 and 3 Torr during warm-up of the wafer prior to barrier metal deposition rather than 5 Torr, which is conventionally used. Using the conventional pressure of 5 Torr the wafer temperature overshoots to about 395° C. before settling to about 380° C. By reducing the pressure to between 2 and 3 Torr, the thermal conductivity between the wafer heater and the wafer is reduced and the overshoot reduced or eliminated. The lower temperature reduces the deposition rate by approximately 10 angstroms over a 15 second deposition, but this is compensated for by an increase in deposition time. However, because the reaction is carried out in the reaction-limited regime, the step coverage will increase when wafer temperature is reduced. The deposition is followed by a N2/H2 plasma-annealing step.

摘要翻译： 实现了通过阻力间歇高开尔文的新方法。 这是通过在预热期间降低室压力来实现的，这防止晶片温度升高到高于约380℃。本发明在阻挡金属沉积之前在晶片预热期间使用2和3托之间的压力 而不是常规使用的5托。 使用5Torr的常规压力，晶片温度在沉降至约380℃之前超过约395℃。通过将压力降低至2和3托之间，晶片加热器和晶片之间的热导率降低，并且 超调减少或消除。 较低的温度在15秒沉积时将沉积速率降低约10埃，但是这通过沉积时间的增加来补偿。 然而，由于反应在反应限制状态下进行，所以当晶片温度降低时，阶跃覆盖将增加。 沉积之后是N2 / H2等离子体退火步骤。

公开(公告)号：US20080111238A1

公开(公告)日：2008-05-15

申请号：US11558342

申请日：2006-11-09

申请人： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

发明人： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K dielectric layer and the low-K dielectric layer to the interconnect layer, depositing an interconnect metal in the opening, and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

摘要翻译： 提供一种集成电路处理系统，包括提供具有集成电路的衬底，在集成电路上形成互连层，在互连层上施加低K电介质层，在低K电介质层上施加超低K电介质层 电介质层，通过超低K电介质层和低K电介质层形成开口到互连层，在开口中沉积互连金属，并对互连金属和超低K电介质层进行化学机械抛光 。

公开(公告)号：US07749894B2

公开(公告)日：2010-07-06

申请号：US11558342

申请日：2006-11-09

申请人： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

发明人： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K dielectric layer and the low-K dielectric layer to the interconnect layer, depositing an interconnect metal in the opening, and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

摘要翻译： 提供一种集成电路处理系统，包括提供具有集成电路的衬底，在集成电路上形成互连层，在互连层上施加低K电介质层，在低K电介质层上施加超低K电介质层 电介质层，通过超低K电介质层和低K电介质层形成开口到互连层，在开口中沉积互连金属，并对互连金属和超低K电介质层进行化学机械抛光 。

公开(公告)号：US06995087B2

公开(公告)日：2006-02-07

申请号：US10328512

申请日：2002-12-23

申请人： Wuping Liu ,  Juan Boon Tan ,  Bei Chao Zhang ,  Alan Cuthbertson

发明人： Wuping Liu ,  Juan Boon Tan ,  Bei Chao Zhang ,  Alan Cuthbertson

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76811 ,  H01L21/76813

摘要： An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.

摘要翻译： 集成电路制造方法包括提供基底，形成第一导体，形成第一阻挡层，形成第一介电层，形成掩模层。 该方法还包括在掩模层中形成第一通孔，在掩模层中形成第一沟槽开口，同时在掩模层下方的层中形成第二通孔，并形成穿过掩模层的第二沟槽开口， 在掩模层下面的层中并且同时在掩模层下方的另一层中形成第三通孔。 该方法还包括使用第三通孔开口和掩模层去除第一阻挡层以形成沟槽和通孔，以及用导体填充沟槽和通孔以形成与第一导体接触的沟槽和通孔导体。

公开(公告)号：US07372156B2

公开(公告)日：2008-05-13

申请号：US11174805

申请日：2005-07-05

申请人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

发明人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

IPC分类号： H01L29/40

CPC分类号： H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

摘要： An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.

摘要翻译： 对准的双镶嵌开口结构，包括以下。 具有形成在其上的金属结构的结构。 金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。 在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。 下通道开口与上沟槽开口连通。 其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。

公开(公告)号：US06967156B2

公开(公告)日：2005-11-22

申请号：US10690998

申请日：2003-10-22

申请人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

发明人： Yeow Kheng Lim ,  Wuping Liu ,  Tae Jong Lee ,  Bei Chao Zhang ,  Juan Boon Tan ,  Alan Cuthbertson ,  Chin Chuan Neo

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L29/06

CPC分类号： H01L21/76807 ,  H01L21/76829 ,  H01L21/76834

摘要： A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. Simultaneously patterning the patterned middle dielectric material layer using the patterned upper dielectric layer as a mask to form an inchoate upper trench opening; and the lower dielectric material layer using the patterned mask layer and the patterned middle etch stop layer as masks to form an inchoate lower via opening aligned with the inchoate upper trench opening.

摘要翻译： 一种形成对准的双镶嵌开口的方法，包括以下顺序步骤。 在金属结构上形成层叠。 层叠层按升序包括底蚀刻停止层; 下介电材料层; 中间蚀刻停止层; 中间介电材料层; 和上介电层。 图案化的掩模层形成在图案化的上介电层上，留下图案化的上介电层的暴露的相对部分。 使用图案化掩模层和上介电层的暴露部分作为掩模，将中介电材料层图案化以形成开口。 使用图案化的上电介质层作为掩模，同时对图案化的中间介电材料层进行图案化以形成初始上沟槽开口; 并且使用图案化掩模层和图案化的中间蚀刻停止层作为掩模的下部电介质材料层形成与前述上部沟槽开口对准的开口下部通孔。

公开(公告)号：US08716856B2

公开(公告)日：2014-05-06

申请号：US13565748

申请日：2012-08-02

申请人： Juan Boon Tan ,  Yeow Kheng Lim ,  Soh Yun Siah ,  Wei Liu ,  Shunqiang Gong

发明人： Juan Boon Tan ,  Yeow Kheng Lim ,  Soh Yun Siah ,  Wei Liu ,  Shunqiang Gong

IPC分类号： H01L23/52

CPC分类号： H01L23/49827 ,  H01L23/147 ,  H01L23/481 ,  H01L23/58 ,  H01L2224/16225

摘要： Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through silicon via (TSV) contacts.

摘要翻译： 公开了用于形成半导体器件的半导体器件和方法。 该半导体器件包括一个管芯。 模具包括具有第一和第二主表面的模具基板。 半导体器件包括设置在管芯衬底的第二主表面下方的功率模块。 电源模块通过硅通孔（TSV）触点电连接到管芯。

公开(公告)号：US08466062B2

公开(公告)日：2013-06-18

申请号：US13287220

申请日：2011-11-02

申请人： Yue Kang Lu ,  Shaoning Yuan ,  Yeow Kheng Lim ,  Juan Boon Tan

发明人： Yue Kang Lu ,  Shaoning Yuan ,  Yeow Kheng Lim ,  Juan Boon Tan

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014

摘要： Generally, the subject matter disclosed herein relates to interconnect structures used for making electrical connections between semiconductor chips in a stacked or 3D chip configuration, and methods for forming the same. One illustrative method disclosed herein includes forming a conductive via element in a semiconductor substrate, wherein the conductive via element is formed from a front side of the semiconductor substrate so as to initially extend a partial distance through the semiconductor substrate. The illustrative method also includes forming a via opening in a back side of the semiconductor substrate to expose a surface of the conductive via element, and filling the via opening with a layer of conductive contact material.

摘要翻译： 通常，本文公开的主题涉及用于在堆叠或3D芯片配置中进行半导体芯片之间的电连接的互连结构及其形成方法。 本文公开的一种说明性方法包括在半导体衬底中形成导电通孔元件，其中导电通孔元件由半导体衬底的前侧形成，以便首先延伸穿过半导体衬底的部分距离。 该说明性方法还包括在半导体衬底的背面形成通孔，以暴露导电通孔元件的表面，并用导电接触材料层填充通孔开口。