公开(公告)号：US06444550B1

公开(公告)日：2002-09-03

申请号：US09640177

申请日：2000-08-17

Applicant: Ming-Yin Hao ,  Emi Ishida

Inventor： Ming-Yin Hao ,  Emi Ishida

IPC: H01L21425

CPC classification number: H01L29/105 ,  H01L21/268 ,  Y10S438/914

Abstract: A semiconductor device having a retrograde channel profile is achieved by forming a retrograde impurity region in the surface portion of a semiconductor substrate, and subsequently forming a semiconductor layer on the retrograde impurity region at a predetermined thickness. The thickness of the semiconductor layer is controlled to localize the retrograde impurity region and its impurity concentration peak at a predetermined depth, thereby reducing the device's susceptibility to “reverse short channel effects.”

Abstract translation: 具有逆行通道轮廓的半导体器件通过在半导体衬底的表面部分中形成逆向杂质区域，随后在逆向杂质区域上以预定厚度形成半导体层来实现。 控制半导体层的厚度以将逆向杂质区域和其杂质浓度峰值定位在预定深度，从而减少器件对“反向短沟道效应”的敏感性。

公开(公告)号：US06426279B1

公开(公告)日：2002-07-30

申请号：US09598911

申请日：2000-06-22

Applicant: Carl Huster ,  Emi Ishida

Inventor： Carl Huster ,  Emi Ishida

IPC: H01L21425

CPC classification number: H01L29/105 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26506 ,  H01L29/6659

Abstract: A semiconductor device exhibiting a super-steep retrograde channel profile to reduce susceptibility to “latch up” is achieved by forming a high impurity concentration layer on a semiconductor substrate and forming a diffusion cap layer near the surface of the high impurity concentration layer. Subsequently, a low impurity concentration layer is formed on the diffusion cap layer of the high impurity concentration layer. The diffusion cap layer formed between the high and low impurity concentration layers substantially prevents the impurities contained in the high impurity concentration layer from diffusing into the overlying low impurity concentration layer, thereby achieving a super-steep retrograde channel profile.

Abstract translation: 通过在半导体衬底上形成高杂质浓度层并在高杂质浓度层的表面附近形成扩散覆盖层，实现了表现出陡峭逆向沟道轮廓以减小“闩锁”敏感性的半导体器件。 接着，在高杂质浓度层的扩散覆盖层上形成低杂质浓度层。 形成在高杂质浓度层和低杂质浓度层之间的扩散帽层基本上防止了高杂质浓度层中所含的杂质扩散到上覆的低杂质浓度层中，从而实现了超陡逆向沟道轮廓。

公开(公告)号：US06395606B1

公开(公告)日：2002-05-28

申请号：US09357918

申请日：1999-07-21

Applicant: Carl R. Huster ,  Ognjen Milic-Strkalj ,  Emi Ishida

Inventor： Carl R. Huster ,  Ognjen Milic-Strkalj ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/66553

Abstract: A MOS semiconductor device is formed with reduced parasitic junction capacitance and reduced gate resistance. Embodiments include forming oxide sidewall spacers on side surfaces of openings in a nitride layer exposing the substrate, and performing a channel implant. A thin gate oxide layer is then thermally grown on the exposed portion of the substrate, and a relatively thin polysilicon layer is deposited on the gate oxide layer and the spacers. A metal layer, such as tungsten, is then deposited filling the opening, and planarized, as by chemical-mechanical polishing, using the nitride layer as a polish stop. Source/drain regions are thereafter formed by ion implantation, and the source/drain regions are silicided. The sidewall spacers and the nitride layer block the channel implant from the source/drain areas, thereby reducing parasitic junction capacitance, and the metal layer extending from above the gate oxide layer to the top of the gate reduces gate resistance, thereby increasing the switching speed of the finished device.

Abstract translation: 形成具有降低的寄生结电容和减小的栅极电阻的MOS半导体器件。 实施例包括在露出衬底的氮化物层中的开口的侧表面上形成氧化物侧壁间隔物，以及执行沟道植入。 然后在衬底的暴露部分上热生长薄的栅极氧化物层，并且在栅极氧化物层和间隔物上沉积相对薄的多晶硅层。 然后沉积诸如钨的金属层，填充开口，并且通过化学机械抛光使用氮化物层作为抛光停止来平坦化。 之后通过离子注入形成源极/漏极区，并且源/漏区被硅化。 侧壁间隔物和氮化物层阻挡从源极/漏极区域的沟道注入，由此减小寄生结电容，并且从栅极氧化物层上方延伸到栅极顶部的金属层降低栅极电阻，从而增加开关速度 的成品设备。

公开(公告)号：US06355528B1

公开(公告)日：2002-03-12

申请号：US09426911

申请日：1999-10-26

Applicant: Emi Ishida ,  Scott Luning ,  Tim Thurgate

Inventor： Emi Ishida ,  Scott Luning ,  Tim Thurgate

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/26586 ,  H01L21/28141 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  Y10S438/947

Abstract: A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.

Abstract translation: 在衬底上形成窄槽。 为了形成这样的窄槽，在基板上形成第一材料，第一材料具有侧壁。 形成邻接侧壁的间隔物。 随后，与间隔物相邻地形成第二材料。 去除间隔物，留下第一材料和第二材料之间的凹槽。 在一个实施例中，槽被填充用于诸如门的窄特征的材料，并且第一材料和第二材料被去除。 结果，形成具有由间隔物的宽度限定的长度的门或其他窄特征。 在另一个实施例中，通过小凹槽执行植入物，导致小的局部植入物。

公开(公告)号：US06245623B1

公开(公告)日：2001-06-12

申请号：US09187431

申请日：1998-11-06

Applicant: Dong-Hyuk Ju ,  Emi Ishida

Inventor： Dong-Hyuk Ju ,  Emi Ishida

IPC: H01L218236

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L21/823814

Abstract: A CMOS semiconductor device having shallow source/drain junctions is formed by ion implanting antimony to form lightly doped source/drain regions of an N-channel transistor, thereby reducing channeling for a shallower projected junction depth as compared to conventional N-type impurity implantations. Upon growing a thermal oxide screen layer to protect the substrate from subsequent ion implantations, the implanted antimony experiences oxidation-retarded diffusion, further reducing the projected junction depth. After ion implanting N-type impurities to form moderately or heavily doped source/drain regions and activation annealing, the resulting semiconductor device exhibits the desirably shallow LDD junctions.

Abstract translation: 具有浅源极/漏极结的CMOS半导体器件通过离子注入锑形成，以形成N沟道晶体管的轻掺杂源极/漏极区域，从而与传统的N型杂质注入相比减少了较浅的投影结深度的沟道。 当生长热氧化物屏幕层以保护衬底免于随后的离子注入时，注入的锑经历氧化延迟扩散，进一步降低了投影的结深度。 在离子注入N型杂质以形成适度或重掺杂的源极/漏极区域和激活退火之后，所得的半导体器件表现出期望的浅的LDD结。

公开(公告)号：US5904575A

公开(公告)日：1999-05-18

申请号：US799153

申请日：1997-02-14

Applicant: Emi Ishida ,  Xiao-Yu Li ,  Sunil D. Mehta

Inventor： Emi Ishida ,  Xiao-Yu Li ,  Sunil D. Mehta

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/316 ,  H01L21/8234 ,  H01L27/115 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/0231 ,  H01L21/02312 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/31662 ,  H01L21/823462 ,  H01L27/115 ,  Y10S148/126 ,  Y10S438/981

Abstract: A method for forming an oxide on the surface of a semiconductor substrate. The method includes the steps of: placing the semiconductor substrate in an atmosphere containing an atmosphere of an oxide growth inhibiting compound; applying laser energy to at least a first portion of the substrate; and forming the oxide on the surface of the substrate by heating the substrate. In a further aspect of the invention, the method comprises applying laser energy through a patterned, reflective reticle. Alternatively, prior to the step of placing, a reflective mask layer may be applied to the surface of the semiconductor substrate. In addition, the invention comprises an EEPROM memory cell having a program junction region in a semiconductor substrate. The cell comprises at least a first program junction provided in the silicon substrate and a floating gate having a portion positioned over the program junction. In addition, an oxide layer is positioned between the program junction and the floating gate, the gate oxide formed by a single thermal oxidation step to have at least a first oxide thickness and a second oxide thickness due to gas immersion laser doped nitrogen underlying a region of the oxide having said at least first oxide thickness.

Abstract translation: 一种在半导体衬底的表面上形成氧化物的方法。 该方法包括以下步骤：将半导体衬底放置在含有氧化物生长抑制化合物气氛的气氛中; 将激光能量施加到所述衬底的至少第一部分; 以及通过加热衬底在衬底的表面上形成氧化物。 在本发明的另一方面，该方法包括通过图案化的反射光罩施加激光能量。 或者，在放置步骤之前，可以将反射掩模层施加到半导体衬底的表面。 此外，本发明包括一个在半导体衬底中具有编程结区的EEPROM存储单元。 该单元包括设置在硅衬底中的至少第一程序段和具有位于程序结上方的部分的浮动栅极。 此外，氧化物层位于程序结和浮置栅极之间，栅极氧化物通过单个热氧化步骤形成，以由于气体浸没激光掺杂氮在下面的区域具有至少第一氧化物厚度和第二氧化物厚度 的具有所述至少第一氧化物厚度的氧化物。

公开(公告)号：US06756600B2

公开(公告)日：2004-06-29

申请号：US09252845

申请日：1999-02-19

Applicant: Che-Hoo Ng ,  Emi Ishida ,  Jaime M. Reyes ,  Jinning Liu ,  Sandeep Mehta

Inventor： Che-Hoo Ng ,  Emi Ishida ,  Jaime M. Reyes ,  Jinning Liu ,  Sandeep Mehta

IPC: H01J3708

CPC classification number: H01J27/08 ,  H01J37/08 ,  H01J2237/31701

Abstract: A method of increasing ion source lifetime in an ion implantation system uses the introduction of an inert gas, such as argon or xenon, into the halide-containing source gas. Inert gas constituents have a cleansing effect in the plasma ambient by enhancing sputtering.

Abstract translation: 在离子注入系统中增加离子源寿命的方法使用惰性气体（例如氩或氙）引入含卤素源气体中。 惰性气体组分通过增强溅射在等离子体环境中具有清洁效果。

公开(公告)号：US06514833B1

公开(公告)日：2003-02-04

申请号：US09667600

申请日：2000-09-22

Applicant: Emi Ishida ,  Che-Hoo Ng

Inventor： Emi Ishida ,  Che-Hoo Ng

IPC: H01L2176

CPC classification number: H01L21/76237 ,  H01L21/823878

Abstract: Semiconductor devices comprising a plurality of active device regions formed in a common semiconductor substrate, e.g., CMOS devices, are formed by utilizing shallow trench isolation (STI) technology enhanced by selectively implanting the bottom surface of the trench with dopant diffusion inhibiting ions prior to filling the trench with a dielectric material and formation of opposite conductivity type well regions on either side of the trench. The inventive methodology effectively reduces or substantially eliminates deleterious counterdoping of the subsequently formed well regions resulting from thermally-induced lateral inter-diffusion of p-type and/or n-type dopant impurities used for forming the well regions.

Abstract translation: 通过利用浅沟槽隔离（STI）技术形成包括形成在公共半导体衬底（例如CMOS器件）中的多个有源器件区域的半导体器件，所述浅沟槽隔离（STI）技术通过在填充之前通过选择性地注入掺杂剂扩散抑制离子的沟槽的底表面来增强 所述沟槽具有电介质材料，并且在沟槽的任一侧上形成相反导电类型的阱区。 本发明的方法有效地减少或基本上消除了由用于形成阱区的p型和/或n型掺杂剂杂质的热诱导的横向相互扩散而导致的随后形成的阱区的有害的反掺杂。

公开(公告)号：US06372582B1

公开(公告)日：2002-04-16

申请号：US09639794

申请日：2000-08-17

Applicant: Richard P. Rouse ,  Ming Yin Hao ,  Emi Ishida ,  Effiong Ibok

Inventor： Richard P. Rouse ,  Ming Yin Hao ,  Emi Ishida ,  Effiong Ibok

IPC: H01L21336

CPC classification number: H01L29/105 ,  H01L21/223 ,  H01L21/26513

Abstract: Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for “latch up” are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate insulator layer.

Abstract translation: 通过去除用于形成沟道区域的逆向形状的铟掺杂浓度分布的残留铟掺杂物，形成具有降低的“闭锁”趋势的亚微米尺寸的硅基MOS型晶体管器件， 硅衬底通过在氧化硅薄栅极绝缘体形成之前的快速热退火工艺。 本发明的方法基本上消除了栅极绝缘体层的有害的铟污染。

公开(公告)号：US06342423B1

公开(公告)日：2002-01-29

申请号：US09667781

申请日：2000-09-22

Applicant: Emi Ishida ,  Srinath Krishnan ,  Ming Yin Hao ,  Effiong Ibok

Inventor： Emi Ishida ,  Srinath Krishnan ,  Ming Yin Hao ,  Effiong Ibok

IPC: H01L218238

CPC classification number: H01L29/6653 ,  H01L21/823468 ,  H01L21/8238 ,  H01L29/6659 ,  H01L29/7833

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of heavily-sloped source/drain junction regions but prior to annealing of the implant for dopant diffusion/activation and lattice damage relaxation. Lightly-or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract translation: 亚微米尺寸的MOS和/或CMOS晶体管通过采用由诸如UV氮化物的材料制成的可移除的侧壁间隔的工艺制造，其易于以其沉积的未增稠的状态蚀刻，但在其热 退火，致密化状态。 通过在植入重度倾斜的源极/漏极结区域之后但是在用于掺杂剂扩散/激活和晶格损伤弛豫的植入物退火之前通过用稀的HF水溶液来蚀刻沉积的未增强的间隔物。 轻微或中度掺杂的浅深度源极/漏极延伸部分在移除间隔物之后被植入和退火。