Equipment for towless skiing on water surface
    12.
    发明授权
    Equipment for towless skiing on water surface 失效
    在水面上无牵引滑雪的设备

    公开(公告)号:US4804345A

    公开(公告)日:1989-02-14

    申请号:US25261

    申请日:1987-03-12

    申请人: Jong S. Lee

    发明人: Jong S. Lee

    IPC分类号: B63B35/83 A63C15/03

    CPC分类号: B63B35/85 B63B35/83

    摘要: Equipment for towless skiing on water surface includes a pair of propulsion sticks having buoyant members at one end and handles at the other end. The buoyant members provide increased thrust against the hydrodynamic resistance of the water, and the shape of the buoyant members permits removal of the buoyant members from the water with little resistance. The equipment also includes a pair of skis comprised of foam material and provided with stabilizing shoulders on both sides of each ski for minimizing the effect of nose diving and rolling of the skis in the surf. The cross-sectional areas of the buoyant members and of the skis are such that maximum propulsion forces are provided. The skis are designed to endow the surf skier with a greater degree of freedom during surf skiing and to enable the skier to ski for longer distances on the water.

    摘要翻译: 在水面上无牵引滑雪的设备包括一对推杆,其一端具有浮力构件,另一端具有手柄。 浮力构件提供相对于水的流体动力阻力的增加的推力,并且浮力构件的形状允许浮力构件从水中以很小的阻力移除。 该设备还包括一对由泡沫材料组成的滑雪板,并在每个滑雪板的两侧设置有稳定肩部,以最小化鼻子潜水和滑雪板在冲浪中的滚动效果。 浮力构件和滑雪板的横截面积使得能够提供最大的推进力。 滑雪板旨在使冲浪滑雪者在冲浪滑雪期间具有更大的自由度,并使滑雪者能够在水面上滑行更长的距离。

    Coin Sorting Apparatus
    13.
    发明申请
    Coin Sorting Apparatus 审中-公开
    硬币分拣装置

    公开(公告)号:US20070224927A1

    公开(公告)日:2007-09-27

    申请号:US11688411

    申请日:2007-03-20

    申请人: Jong S. Lee

    发明人: Jong S. Lee

    CPC分类号: G07D9/006 G07D9/065

    摘要: A coin sorting apparatus is provided. The coin sorting apparatus includes a main body, a coin sorting unit, a transport unit, a casing tube, a coin tube, and a pressing unit. The coin sorting unit is disposed in an upper portion of the main body. The transport unit is disposed in a lower portion of the main body. The casing tube is transported by the transport unit. The coin tube is made of transparent plastic and placed within the casing tube. The pressing unit is disposed in a front portion of the main body. The present invention makes it possible to improve a functionality and usability of the coin sorting apparatus.

    摘要翻译: 提供硬币分类装置。 硬币分类装置包括主体,硬币分类单元,输送单元,套管,硬币管和按压单元。 硬币分类单元设置在主体的上部。 输送单元设置在主体的下部。 套管由运输单元运输。 硬币管由透明塑料制成,放置在套管内。 按压单元设置在主体的前部。 本发明使得可以提高硬币分类装置的功能性和可用性。

    System for cultivating and harvesting beam sprouts
    14.
    发明授权
    System for cultivating and harvesting beam sprouts 失效
    栽培和收获芽苗的系统

    公开(公告)号:US5042195A

    公开(公告)日:1991-08-27

    申请号:US446678

    申请日:1989-12-06

    IPC分类号: A01G31/06

    CPC分类号: A01G31/06 Y02P60/216

    摘要: A system for cultivating and harvesting bean sprouts includes an enclosed container having a door movable between open and closed positions for excluding external light from the interior of the container when the door is in a closed position. A plurality of bean sprout support elements, each of the elements defining an open mesh screen for supporting beans and bean sprouts growing from the beans, are removably stacked within the container in vertical, spaced apart relationship with each other. A cultivating fluid is circulated within the container and over and around the beans and bean sprouts. The bean sprouts are harvested by positioning the bean sprout support elements onto conveyor elements which cause the support elements and bean sprouts to be passed over serving elements which separate fine roots and chaff from the bean sprouts, and the bean sprouts are collected for later use.

    摘要翻译: 用于培育和收获豆芽的系统包括封闭容器,其具有可在打开和关闭位置之间移动的门,用于当门处于关闭位置时排除来自容器内部的外部光。 多个豆芽支撑元件,限定用于支撑从豆生长的豆类和豆芽的开放筛网的每个元件以彼此垂直,间隔开的关系可拆卸地堆叠在容器内。 培养液在容器内并在豆类和豆芽周围和周围循环。 通过将豆芽支撑元件定位到输送机元件上来收获豆芽,该输送机元件使得支撑元件和豆芽通过从豆芽分离细根和谷壳的服务元件,并收集豆芽以备后用。

    Apparatus and method of solder coating integrated circuit leads
    16.
    发明授权
    Apparatus and method of solder coating integrated circuit leads 失效
    焊锡涂层集成电路引线的装置和方法

    公开(公告)号:US4720034A

    公开(公告)日:1988-01-19

    申请号:US928951

    申请日:1986-11-10

    申请人: Jong S. Lee

    发明人: Jong S. Lee

    IPC分类号: H05K3/34 H05K13/04 B05C13/00

    摘要: Desired control of the thickness and composition of a solder coat on the J-leads of an integrated circuit Quad package is obtained by orienting the packages while being solder coated in a "leads-up" orientation as a series of strips mounting the packages are passed through a solder wave of a wave soldering apparatus on a pallet. The Quad or other shaped integrated circuit or other electronic packages which have leads extending exteriorly thereof, thus have the critical lead crest portions coated with substantially the same solder layer thickness and composition. This permits reliable electrical connections between the crest portions of the leads and printed circuit board metal traces (metallization), particularly in surface mounting of the package to a printed circuit board. An additional feature of the invention is a pallet for holding a series of package-holding elongate frames which pallet is used for conveying the packages through the wave soldering apparatus.

    摘要翻译: 期望对集成电路的J引线上的焊料涂层的厚度和组成的控制四重封装是通过将封装定向在以“引导”方向焊接涂覆的情况下获得的,因为安装封装的一系列带通过 通过在托盘上的波峰焊装置的焊波。 具有在其外部延伸的引线的四边形或其他形状的集成电路或其他电子封装,因此具有涂覆有基本上相同的焊料层厚度和组成的临界引线顶部。 这允许引线的顶部和印刷电路板金属迹线(金属化)之间的可靠电连接,特别是在封装到印刷电路板的表面安装中。 本发明的附加特征是用于保持一系列包装保持细长框架的托盘,该托盘用于通过波峰焊装置输送包装。

    Method of measuring height of foot arch
    17.
    发明授权
    Method of measuring height of foot arch 失效
    足弓高度测量方法

    公开(公告)号:US06293026B1

    公开(公告)日:2001-09-25

    申请号:US09456576

    申请日:1999-12-08

    IPC分类号: A61B5107

    CPC分类号: A43B7/28 A43D1/022 G01B1/00

    摘要: A method of measuring the height of a foot arch precisely and easily using two essential heights of the foot arch is disclosed. In the method, a foot cast is primarily cast by pouring plaster into a foot mold. Thereafter, a first intersecting point and a second intersecting point are determined. The first intersecting point is determined by making a first line and a third line intersect. The second intersecting point is determined by making a second line and the third line intersect. The first line is a straight line extending from the center of the second toe to the center of the heel end. The second line is a straight line extending from the center of the big toe to a point spaced apart inwardly from the center of the heel end by ⅛ of the total distance of the heel end. The third line is a center line of the transverse arch of the foot. Finally, a first height and a second height are measured while the foot pattern is set in an upright position. The first height is defined between a flat base level and the first intersecting point, while the second height is defined between the base level and the second intersecting point.

    摘要翻译: 公开了一种使用足弓的两个基本高度精确且容易地测量足弓的高度的方法。 在该方法中,脚浇铸主要是通过将石膏浇注到脚模中来铸造的。 此后,确定第一交点和第二交点。 通过使第一行和第三行相交来确定第一个相交点。 通过制作第二行和第三行相交来确定第二个相交点。 第一行是从第二脚趾的中心延伸到脚后跟中心的直线。 第二行是从大脚趾的中心延伸到从脚跟端的中心向内分开的距离为脚跟端的总距离的直线。 第三行是脚的横向拱的中心线。 最后,在将脚图案设置在直立位置时,测量第一高度和第二高度。 第一高度被限定在平坦的基准水平和第一个相交点之间,而第二个高度是在基准水平和第二个相交点之间定义的。

    Noise reducing output buffer circuit for an integrated circuit
    18.
    发明授权
    Noise reducing output buffer circuit for an integrated circuit 失效
    用于集成电路的降噪输出缓冲电路

    公开(公告)号:US5057711A

    公开(公告)日:1991-10-15

    申请号:US530819

    申请日:1990-05-30

    CPC分类号: H03K19/01742 H03K19/00361

    摘要: An output buffer circuit for an integrated circuit for outputting an amplified signal from a sense amplifier which senses information stored in a memory cell of random access memory for improving operation of the integrated circuit is disclosed. The output buffer circuit comprises NAND gates ND1, ND2 operatively connected to the output of the sense amplifier to receive first and second output signals S1, S2, and operatively connected to receive a control signal .phi.1 from the integrated circuit which operates the memory cell to read. A MOSFET Q1 and a MOSFET Q2 are utilized with both MOSFETs turning on or off depending upon the signals applied to their gates. An output loading capacitor CL is operatively connected to the junction P4 and to the ground. A logic combination means 10 connected to junctions P1, P2 performs a logical combination of the signal applied through the junction P4 and the control signal .phi.1 applied to the input points of the logic combination means. An output means 20 is connected between the logic combination means 10 and the junction P4, thereby controlling the output level of the output buffer circuit to a middle level depending upon the signal from the logic combination means.

    摘要翻译: 公开了一种用于从感测放大器输出放大信号的集成电路的输出缓冲电路,其感测存储在随机存取存储器的存储单元中的信息,以改善集成电路的操作。 输出缓冲器电路包括可操作地连接到读出放大器的输出的NAND门ND1,ND2,以接收第一和第二输出信号S1,S2,并且可操作地连接以从操作存储器单元的集成电路接收控制信号phi 1 读。 根据施加到其栅极的信号,使用MOSFET Q1和MOSFET Q2,两个MOSFET导通或关断。 输出负载电容器CL可操作地连接到接点P4和接地。 连接到结点P1,P2的逻辑组合装置10执行通过结点P4施加的信号和施加到逻辑组合装置的输入点的控制信号phi 1的逻辑组合。 输出装置20连接在逻辑组合装置10和接点P4之间,从而根据来自逻辑组合装置的信号将输出缓冲器电路的输出电平控制到中间电平。

    Video codec including pipelined processing elements
    19.
    发明授权
    Video codec including pipelined processing elements 失效
    视频编解码器,包括流水线处理元件

    公开(公告)号:US5046080A

    公开(公告)日:1991-09-03

    申请号:US529887

    申请日:1990-05-29

    摘要: A videophone system for providing videophone service within narrow band digital network, based on pipelined processing elements, includes source codec means coupled to the image bus, including numerous processing elements of which processing element has DSP (Digital Signal Processor) module, local memory module coupled to the DSP module, FIFO (First Input First Output) memory module coupled to the DSP module and the local memory module, and image bus interface module coupled to the DSP module and the local memory module and the image bus, wherein communications between the processor elements is performed via the pipeline and common memory means coupled to the VME bus and the image bus, for storing message data for synchronization and communication between the processing elements.

    摘要翻译: 一种用于在窄带数字网络内基于流水线处理元件提供可视电话服务的视频电话系统包括耦合到图像总线的源编解码器装置,包括处理元件具有DSP(数字信号处理器)模块,本地存储器模块耦合的多个处理元件 耦合到DSP模块和本地存储器模块的FIFO(第一输入第一输出)存储器模块,以及耦合到DSP模块和本地存储器模块和图像总线的图像总线接口模块,其中处理器 通过流水线执行元件,并且耦合到VME总线和图像总线的公共存储器装置,用于存储用于在处理元件之间进行同步和通信的消息数据。

    Apparatus and method of solder coating integrated circuit leads

    公开(公告)号:US4657172A

    公开(公告)日:1987-04-14

    申请号:US794038

    申请日:1985-10-31

    申请人: Jong S. Lee

    发明人: Jong S. Lee

    IPC分类号: H01L23/50 H05K3/34 H05K13/04

    摘要: Desired control of the thickness and composition of a solder coat on the J-leads of an integrated circuit Quad package is obtained by orienting the packages while being solder coated in a "leads-up" orientation as a series of strips mounting the packages are passed through a solder wave of a wave soldering apparatus on a pallet. The Quad or other shaped integrated circuit or other electronic packages which have leads extending exteriorly thereof, thus have the critical lead crest portions coated with substantially the same solder layer thickness and composition. This permits reliable electrical connections between the crest portions of the leads and printed circuit board metal traces (metallization), particularly in surface mounting of the package to a printed circuit board. An additional feature of the invention is a pallet for holding a series of package-holding elongate frames which pallet is used for conveying the packages through the wave soldering apparatus.