公开(公告)号：US06633451B1

公开(公告)日：2003-10-14

申请号：US09426435

申请日：1999-10-25

Applicant: Timothy J. Chainer ,  Bucknell C. Webb ,  Mark D. Schultz ,  Edward J. Yarmchuk

Inventor： Timothy J. Chainer ,  Bucknell C. Webb ,  Mark D. Schultz ,  Edward J. Yarmchuk

IPC: G11B2102

CPC classification number: G11B5/59633

Abstract: A method is provided for writing a servo-pattern on a storage medium. According to the method, first timing marks are written at a first radial position of the storage medium, and the head is moved to a second radial position. Time intervals between selected pairs of the first timing marks are measured, and other timing marks are written at the second radial position of the storage medium. The measuring step is performed after the moving step. In one preferred method, the steps of moving, measuring, and writing other timing marks are repeated until the servo-pattern is written on an entire surface of the storage medium. A method is also provided for generating an initial aligned pattern of timing marks for self-servo-writing on a storage medium.

Abstract translation: 提供一种用于将伺服图案写入存储介质的方法。 根据该方法，将第一定时标记写入存储介质的第一径向位置，并且将头移动到第二径向位置。 测量所选择的第一定时标记对之间的时间间隔，并且其他定时标记被写入存储介质的第二径向位置。 测量步骤在移动步骤之后进行。 在一个优选的方法中，重复移动，测量和写入其它定时标记的步骤，直到伺服图案被写入存储介质的整个表面。 还提供了一种用于在存储介质上产生用于自伺服写入的定时标记的初始对准图案的方法。

公开(公告)号：US5844742A

公开(公告)日：1998-12-01

申请号：US735924

申请日：1996-10-24

Applicant: Edward John Yarmchuk ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Timothy Joseph Chainer

Inventor： Edward John Yarmchuk ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Timothy Joseph Chainer

IPC: G11B5/012 ,  G11B5/55 ,  G11B5/596 ,  G11B21/10 ,  G11B5/02

CPC classification number: G11B5/5534 ,  G11B21/10 ,  G11B21/106 ,  G11B5/59633 ,  G11B5/59644

Abstract: During a write revolution of a storage medium, a transition is written on the storage medium while servoing on another transition previously recorded on the storage medium. During that write revolution, a position error signal corresponding to the position error of the transducer relative to the previously recorded transition is determined. That position error signal is then stored, during the write revolution, to be used in computing a reference track value associated with the transition being written in order to correct for the position error

Abstract translation: 在存储介质的写入转动期间，在先前记录在存储介质上的另一个转换上进行伺服处理，在存储介质上写入转换。 在该写入旋转期间，确定对应于换能器相对于先前记录的转变的位置误差的位置误差信号。 然后，在写入旋转期间，存储该位置误差信号以用于计算与被写入的转换相关联的参考轨迹值，以便校正位置误差

公开(公告)号：US07545648B2

公开(公告)日：2009-06-09

申请号：US12055263

申请日：2008-03-25

Applicant: John P. Karidis ,  Mark D. Schultz ,  Bucknell C. Webb

Inventor： John P. Karidis ,  Mark D. Schultz ,  Bucknell C. Webb

IPC: H05K7/20 ,  H01L23/34

CPC classification number: H01L23/433 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An information processing system includes: a processor; a memory; an input/output subsystem; and a bus coupled to the processor, the memory and the input/output subsystem. The system further includes a cooling structure for cooling the processor. The cooling structure consists of: a compressible backing; a plurality of rigid copper elements disposed between the backing and the processor; a first conformable heat-conducting layer disposed over the processor; a second conformable heat-conducting layer disposed between the compressible backing and the rigid elements; a liquid coolant; and a seal for containing the liquid coolant.

Abstract translation: 一种信息处理系统，包括：处理器; 记忆 输入/输出子系统; 以及耦合到处理器，存储器和输入/输出子系统的总线。 该系统还包括用于冷却处理器的冷却结构。 冷却结构包括：可压缩背衬; 设置在背衬和处理器之间的多个刚性铜元件; 设置在所述处理器上的第一适形导热层; 设置在可压缩背衬和刚性元件之间的第二适形导热层; 液体冷却剂; 以及用于容纳液体冷却剂的密封件。

公开(公告)号：US5991115A

公开(公告)日：1999-11-23

申请号：US211138

申请日：1998-12-14

Applicant: Timothy Joseph Chainer ,  Anthony Paul Praino ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Edward John Yarmchuk

Inventor： Timothy Joseph Chainer ,  Anthony Paul Praino ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Edward John Yarmchuk

IPC: G11B5/55 ,  G11B5/596 ,  G11B19/04 ,  G11B21/10

CPC classification number: G11B19/04 ,  G11B21/106 ,  G11B5/5565 ,  G11B5/59633

Abstract: Improvements in placement of timing patterns in self servo writing include correcting for random and systematic errors due to geometric effects. In a disk drive having a recording head with separate read and write elements, a method for determining separation between the elements and for correcting for such errors as a function of skew angle between the head and the disk. Errors resulting from misalignment and non-parallelism of the elements as well as misalignment of the head on it its actuator are also detected and corrected. Errors due to changes in rotational velocity of the disk and misplacement of timing patterns with respect to adjacent timing patterns are detected and corrected. In general, a single revolution process may be used to both write and detect random errors on each track and corrected on subsequent tracks.

Abstract translation: 自动写入中定时模式布置的改进包括纠正由于几何效应引起的随机和系统误差。 在具有具有分离的读取和写入元件的记录头的磁盘驱动器中，确定元件之间的间隔并用于校正这种错误的方法，其作为头部和盘之间的歪斜角的函数。 元件的不对准和不平行度导致的误差以及头部在其致动器上的未对准性也被检测和校正。 检测并纠正由于盘的旋转速度的变化引起的错误和定时图案相对于相邻的定时图案的错位。 通常，可以使用单次旋转处理来写入和检测每个轨道上的随机误差并在随后的轨道上进行校正。

公开(公告)号：US08801352B2

公开(公告)日：2014-08-12

申请号：US13207609

申请日：2011-08-11

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L21/00

CPC classification number: H01L21/67132

Abstract: Pick and place tape release techniques and tools that allow thin, fragile semiconductor dies to be removed from wafer tape with reduced tape release forces applied to the semiconductor dies. For example, a method for removing semiconductor die from wafer tape includes mounting a wafer ring having wafer tape and one or more dies attached to the wafer tape, and aligning an ejector pin assembly under a target die to be removed from the wafer tape. The ejector pin assembly includes a vacuum housing, an ejector pin, a suction plate, and an aperture formed in the suction plate in alignment with the ejector pin. A vacuum is generated in the vacuum housing to draw the tape against a surface of the suction plate. The ejector pin is extended through the vacuum housing out from the aperture of the suction plate to push against a backside of the target die and release the tape from the backside of the target die, and as the tape is released from the backside of the target die, the tape is drawn down against the suction plate by suction force of the vacuum.

Abstract translation: 拾取和放置磁带释放技术和工具，其允许薄的，脆弱的半导体管芯从晶片带去除，同时减小施加到半导体管芯上的剥离力。 例如，从晶片带除去半导体管芯的方法包括安装具有晶片带的晶片环和安装在晶片带上的一个或多个管芯，以及使靶组件下方的顶针组件对准晶片带。 顶针组件包括真空壳体，顶针，吸板和形成在吸板中的与顶针对准的孔。 在真空壳体中产生真空以将带材吸附在吸盘的表面上。 顶针从吸板的孔径延伸穿过真空壳体，以推压目标管芯的背面并从目标管芯的背面释放带，并且当带从靶的背面释放时 模具，胶带通过真空的吸力被吸引到吸盘上。

公开(公告)号：US08736277B2

公开(公告)日：2014-05-27

申请号：US13369872

申请日：2012-02-09

Applicant: Dennis G. Manzer ,  Bucknell C. Webb

Inventor： Dennis G. Manzer ,  Bucknell C. Webb

IPC: G01R31/06

CPC classification number: H01F38/00 ,  H01F2038/006

Abstract: Systems, methods and devices directed to transformers are disclosed. One transformer system includes a set of transformer cells and a controller. The set of transformer cells is coupled in series to form a series coupling, where each transformer cell includes at least one first coil and at least one second coil. The second coil is configured to receive electrical energy from the first coil through magnetic interaction. The controller is configured to modify electrical aspects at ends of the series coupling by independently driving the transformer cells such that at least one of the transformer cells is driven differently from at least one other transformer cell in the set.

Abstract translation: 公开了涉及变压器的系统，方法和装置。 一个变压器系统包括一组变压器单元和一个控制器。 该组变压器单元串联耦合以形成串联耦合，其中每个变压器单元包括至少一个第一线圈和至少一个第二线圈。 第二线圈被配置为通过磁相互作用从第一线圈接收电能。 控制器被配置为通过独立地驱动变压器单元来修改串联耦合的端部处的电气方面，使得变压器单元中的至少一个与组中的至少一个其它变压器单元不同地被驱动。

公开(公告)号：US20140061853A1

公开(公告)日：2014-03-06

申请号：US13597412

申请日：2012-08-29

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01F5/00 ,  H01L21/02 ,  H01L29/86

CPC classification number: H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure.

Abstract translation: 提供具有层压的磁 - 绝缘体堆叠结构的诸如电感器，变压器等的半导体集成磁性器件，其中使用电镀技术形成层叠的磁性 - 绝缘体堆叠结构。 例如，集成层叠磁性装置包括在基板上形成交替的磁性层和绝缘层的多层堆叠结构，其中多层堆叠结构中的每个磁性层通过绝缘层与多层堆叠结构中的另一磁性层分离，以及 局部短路结构，以将多层堆叠结构中的每个磁性层电连接到多层堆叠结构中的下面的磁性层，以便利用叠层中的下面的导电层（磁性或种子层）作为电阴极来促进磁性层的电镀 /阳极，用于堆叠结构中的每个电镀磁性层。

公开(公告)号：US20130093032A1

公开(公告)日：2013-04-18

申请号：US13272485

申请日：2011-10-13

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L29/82 ,  H01L21/02

CPC classification number: H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor trench inductor and transformer structures are provided, which include thin film conductive layers and magnetic layers formed within trenches etched in semiconductor substrates. Semiconductor trench devices effectively provide vertical oriented inductor and transformer structures whereby conductive coils and magnetic layers are vertically oriented on edge within trenches, thereby providing a space-saving compact design, and which allows the conductive layers within the trench to be enclosed by magnetic material, thereby providing a density of magnetic material that increases the storable energy density.

Abstract translation: 提供半导体沟槽电感器和变压器结构，其包括形成在半导体衬底中蚀刻的沟槽内的薄膜导电层和磁性层。 半导体沟槽器件有效地提供垂直取向的电感器和变压器结构，由此导电线圈和磁性层在沟槽内的边缘垂直取向，从而提供节省空间的紧凑设计，并且允许沟槽内的导电层被磁性材料包围， 从而提供增加可储存能量密度的磁性材料的密度。

公开(公告)号：US08102236B1

公开(公告)日：2012-01-24

申请号：US12968118

申请日：2010-12-14

Applicant: Robert E. Fontana, Jr. ,  William J. Gallagher ,  Philipp Herget ,  Bucknell C. Webb

Inventor： Robert E. Fontana, Jr. ,  William J. Gallagher ,  Philipp Herget ,  Bucknell C. Webb

IPC: H01F5/00

CPC classification number: H01F17/0006 ,  H01F3/14

Abstract: A thin film inductor according to one embodiment includes one or more arms; one or more conductors passing through each arm; a first ferromagnetic yoke wrapping partially around the one or more conductors in a first of the one or more arms, the first ferromagnetic yoke comprising a magnetic top section, a magnetic bottom section, and via regions positioned on opposites sides of the one or more conductors in the first of the one or more arms, wherein the magnetic top section and magnetic bottom section are coupled together through a low reluctance path in the via regions; and one or more non-magnetic gaps between the top section and the bottom section in at least one of the via regions. Additional systems and methods are also provided.

Abstract translation: 根据一个实施例的薄膜电感器包括一个或多个臂; 穿过每个臂的一个或多个导体; 所述第一铁磁磁轭围绕所述一个或多个臂中的第一个中的所述一个或多个导体包围，所述第一铁磁轭包括磁性顶部，磁性底部部分和位于所述一个或多个导体的相​​对侧上的通孔区域 在一个或多个臂中的第一个中，其中磁性顶部部分和磁性底部部分通过通孔区域中的低磁阻路径耦合在一起; 以及在至少一个通孔区域中的顶部和底部之间的一个或多个非磁性间隙。 还提供了附加的系统和方法。

公开(公告)号：US20080265428A1

公开(公告)日：2008-10-30

申请号：US11740325

申请日：2007-04-26

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L23/488

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13012 ,  H01L2224/13025 ,  H01L2924/00014 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09854 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method of modifying via and solder ball shapes for maximizing semiconductor chip or silicon carrier strengths relative to thermal expansion and bending load zero points. The method entails modifying circular annular vias into elliptical annular vias so as to reduce stress concentration factors in the chip or carrier at the vias and solder balls. The reduction in the stress concentration is effected in the semiconductor chip or silicon carrier in regions proximate the vias and in wiring layers at the ends of the vias.

Abstract translation: 一种改变通孔和焊球形状的方法，用于相对于热膨胀和弯曲载荷零点使半导体芯片或硅载体的强度最大化。 该方法需要将圆形环形通孔修改为椭圆形环形通孔，以便减少通孔和焊球处的芯片或载体中的应力集中系数。 应力集中的降低在半导体芯片或硅载体中在通孔附近的区域和通孔末端的布线层中实现。