Abstract:
The present disclosure provides a mask-pellicle system for lithography patterning. The mask-pellicle system includes a mask substrate; a predefined pattern formed on the transparent pattern; a pellicle configured approximate the transparent substrate; a pellicle frame designed to secure the pellicle; and a stress-absorbing feature configured between the pellicle frame and the mask substrate, to reduce stress of the mask substrate.
Abstract:
A method for splitting a pattern layout including providing the pattern layout having features, checking the pattern layout to determine the features that require splitting, coloring the features that require splitting with a first and second color, resolving coloring conflicts by decomposing the feature with the coloring conflict and coloring the decomposed feature with the first and second color, and generating a first mask with features of the first color and a second mask with features of the second color.
Abstract:
A method and system is disclosed for processing one or more oblique features on a mask or reticle substrate. After aligning the mask or reticle substrate with a predetermined reference system, an offset angle of a feature to be processed on the mask or reticle substrate with regard to either the horizontal or vertical reference direction of the predetermined reference system is determined. The mask or reticle substrate is rotated in a predetermined direction by the offset angle; and the feature on the mask or reticle substrate is processed using the predetermined reference system wherein the feature is processed in either the horizontal or vertical reference direction thereof.
Abstract:
A method of wafer repairing comprises identifying locations and patterns of defective regions in a semiconductor wafer; communicating the locations and patterns of defective regions to a direct-writing tool; forming a photoresist layer on the semiconductor wafer; locally exposing the photoresist layer within the defective regions using an energy beam; developing the photoresist layer on the semiconductor wafer; and wafer-processing the semiconductor wafer under the photoresist layer after exposing and developing.
Abstract:
Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance of the representative of the mask layout by a cost function and a Boltzmann factor, where the cost function is related to the mask layout and a target substrate pattern, and the Boltzmann factor is related to the cost function and the control parameter. The methods repeats the steps of generating the representative and determining acceptance until the mask layout is stabilized. The control parameter is decreased according to an annealing schedule. The generating, determining, repeating, and decreasing steps are reiterated until the mask layout is optimized.
Abstract:
An apparatus for mounting at least one hard pellicle to a mask which includes an enclosure having an interior cavity, demounting means for removing a protective cover from a mask, mounting means for mounting at least one hard pellicle to the mask and conduit means for pumping a light-transmitting gas into the interior cavity between the hard pellicle and the mask.
Abstract:
A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure. Forming the third structure includes independently aligning the first substructure to the first structure and independently aligning the second substructure to the second structure.
Abstract:
A lithography apparatus generates a tunable magnetic field to facilitate processing of photoresist. The lithography apparatus includes a chamber and a substrate stage in the chamber operable to hold a substrate. A magnetic module provides a magnetic field to the substrate on the substrate stage. The magnetic module is configured to provide the magnetic field in a tunable and alternating configuration with respect to its magnitude and frequency. The magnetic field is provided to have a gradient in magnitude along a Z-axis that is perpendicular to the substrate stage to cause magnetically-charged particles disposed over the substrate stage to move up and down along the Z-axis. The lithography apparatus also includes a radiation energy source and an objective lens configured to receive radiation energy from the radiation energy source and direct the radiation energy toward the substrate positioned on the substrate stage.
Abstract:
Immersion lithography system and method using direction-controlling fluid inlets are described. According to one embodiment of the present disclosure, an immersion lithography apparatus includes a lens assembly having an imaging lens disposed therein and a wafer stage configured to retain a wafer beneath the lens assembly. The apparatus also includes a plurality of direction-controlling fluid inlets disposed adjacent to the lens assembly, each direction-controlling fluid inlet in the plurality of direction-controlling fluid inlets being configured to direct a flow of fluid beneath the lens assembly and being independently controllable with respect to the other fluid inlets in the plurality of direction-controlling fluid inlets.
Abstract:
The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning.